Ion Implantation for Silicon Carbide Electronic Devices
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ION IMPLANTATION FOR SILICON CARBIDE ELECTRONIC DEVICES Michael A. Capano Purdue University, School of Electrical and Computer Engineering, West Lafayette, IN ABSTRACT As the demands on electronic systems intended for high temperature, high power or high frequency operation increase, silicon-based electronics are being pushed to its fundamental material limits. Consequently, continued improvement in system level performance for these applications requires new semiconductor materials. Silicon carbide (SiC) is a candidate material for the applications listed above, but considerable materials, processing, and device research are still needed before SiC devices are brought to market. This paper concentrates on ion implantation processing of SiC, and attempts to illustrate specific problems associated with ion implantation. Data from a series of experiments relevant to SiC MOSFETs are presented for this purpose. Ion implants into SiC are discussed first to show how a strategy for improving the acceptor activation ratio from less than 1% to nearly 100% is developed. The annealing temperatures (>1600oC) needed to attain high activation ratios lead to severely roughened surfaces. Results from experiments designed to preserve high-quality surfaces have been encouraging from a purely materials perspective. However, these solutions do not translate into improved transport characteristics for SiC MOSFETs. An investigation of inversion layer mobility in 4H-SiC MOSFETs is presented to illustrate this point.
INTRODUCTION Ion implantation is an important processing step for the fabrication of many silicon carbide (SiC) electronic devices. The effectiveness of an ion implantation step in the fabrication of SiC electronic devices is typically measured by several parameters. These parameters include activation ratio, sheet resistance, and transport characteristics such as electron mobility. To better understand the relevance of these parameters, consider the fabrication of a double-implanted metal-oxide-semiconductor field-effect transistor (DMOSFET) shown in Fig. 1. Two implantations are required for this device: an acceptor implantation (Al or B) to define the p-well, and a donor implantation (N or P) to define the source region. What is required for optimally-performing devices is a high (and controllable) activation ratio in the p-well in order to support a large blocking voltage when the device is ‘off’. Also, a low sheet resistance in the source region is desired to minimize losses caused by high series resistances when the device is ‘on’. The device is turned on by applying a positive voltage to the poly-Si gate, which causes an inversion channel to form near the oxide/SiC interface. Electrons can then flow from the source, through the drift region in the n- SiC epilayer, to the drain on the backside of the device. The thickness of the inversion channel is approximately 100 Å. Therefore, any surface irregularities, such as excessive roughness, may have adverse effects on transport properties within the channel. H6.1.1
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