Lateral Superlattices Fabricated with Interferometric Lithography for Nanoscale Device Applications
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Lateral Superlattices Fabricated with Interferometric Lithography for Nanoscale Device Applications Christopher C. Striemer, Philippe M. Fauchet, and Leonid Tsybeskov Nanoscale Silicon Research Initiative Department of Electrical and Computer Engineering, University of Rochester Rochester, NY 14627-0231, U.S.A. ABSTRACT Two-dimensional periodic arrays of inverted pyramid holes with nanometer scale have been patterned on the surface of a (100) silicon wafer and studied for possible application in nanoscale silicon based devices. The surface patterning employed a simple microelectronic processing scheme in which the standing wave intensity pattern from two interfering 458nm laser beams was used to expose holes in a photoresist layer. Subsequent dry etching through an underlying oxide mask layer, followed by a KOH etching step yielded a highly periodic, large area array of inverted pyramids. The pyramid geometry is formed during the anisotropic KOH etch, which stops at the (111) pyramid walls. Therefore, the tips of all inverted pyramids are formed by the intersection of (111) silicon crystal planes and have identical geometry. This study focuses on the use of these features as templates for the controlled crystallization of amorphous silicon layers and also as electric field concentrating “funnels” in MOS-type structures. We will discuss a proposed device in which silicon nanocrystals will be incorporated into the concentrated electric field region at the tip of each inverted pyramid. With this structure, the charging of identical addressable nanocrystals may be possible, leading to the development of practical nanoscale silicon devices. INTRODUCTION There has been substantial interest in nanoscale Si memories in recent years, both as a replacement for electrically programmable read-only memory (EPROM) and potentially for certain dynamic random access memory (DRAM) applications. The fundamental advantage of nanoscale Si memories is the lower voltage and higher speed of operation compared to the floating gate EPROM. EPROM operates by storing charge on a floating gate by forcing electrons to tunnel through an oxide barrier when a high voltage is applied [1]. The applied voltage required to drive electrons through this oxide onto the gate is dependent on the oxide thickness. Therefore the thickness of this oxide layer must be kept as thin as possible to keep writing voltages low, but must also be thick enough to insure that no hole in the oxide layer exists over the area of the floating gate. Any hole in the oxide will cause the device to fail, because the stored charge could easily leak from the floating gate. However, if this floating gate is replaced by an array of isolated Si nanocrystals, a hole in the oxide would only effect neighboring nanocrystals, and the overall device would not fail. The Si nanocrystals could be charged and discharged similar to the floating gate, but would be less susceptible to catastrophic failure resulting from oxide defects. As a result, the gate oxide thickness could be reduced, allowing
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