Low-Temperature Solid-Phase Epitaxy of Defect-Free Aluminum p + -doped Silicon for Nanoscale Device Applications
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0940-P05-04
Low-Temperature Solid-Phase Epitaxy of Defect-Free Aluminum p+-doped Silicon for Nanoscale Device Applications Yann Civale1, Lis K. Nanver1, Peter Hadley2, Egbert J. G. Goudena1, Henk W. van Zeijl1, and Hugo Schellevis1 1 DIMES - Laboratory of ECTM, Delft University of Technology, Feldmannweg 17, Delft, 2628 CT, Netherlands 2 Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, Delft, 2628 CJ, Netherlands
ABSTRACT A solid phase epitaxy (SPE) technique was developed to grow p+ aluminum-doped crystalline Si in a fully CMOS compatible process. This paper describes the experimental conditions leading to the selective growth of nanoscale single crystals where the location and dimensions are well controlled, even in the sub-100 nm range. The SPE Si crystals are defined by conventional lithography and show excellent electrical characteristics. Fifty-nanometer-thick p+ SPE Si crystals were used to fabricate p+-n-p bipolar junction transistors. The remarkable control of the whole process, even in the sub-100 nm range, make this module directly usable for Si-based nanodevices. INTRODUCTION This work was inspired by the results achieved in the growth of semiconducting nanowires where complex, three dimensional structures have been grown. It is possible to epitaxially grow materials with large lattice mismatches on top of each other in nanowire form since significant strain does not accumulate in small structures. The transitions between the materials are nearly atomically sharp. Another advantage of nanowire growth is that it typically takes place at much lower temperatures than conventional epitaxial growth. Several nanowire growth methods have been developed, such as template-assisted synthesis, laser ablation [1], chemical vapor deposition (CVD) [2], electrochemical deposition [3], and the vapor-liquid-solid (VLS) approach [4-6]. By using these different techniques, a large variety of semiconducting nanowires made of, for example, indium phosphide [7], gallium nitride [8], germanium [9] and silicon [10] have been grown. The most commonly used growth technique is VLS where the nanowires are grown from a vapor-phase Si precursor via a metal catalyst. Due to its physical and chemical properties, gold is frequently used as the catalyst. Gold also has the advantage that it forms eutectic alloys with semiconductor materials at low temperature. However, not all of these growth techniques are compatible with CMOS technology. Materials such as Au or Fe are not compatible with front-end Si processing because they diffuse and deteriorate the device performance. In addition, the ability to control the dimensions and the position of the nanowires, which is an essential requirement for future IC applications, is not provided by some of the existing growth techniques. Moreover, our results may shed some light on a controversy in the literature concerning VLS growth. K.A. Dick et al. [11] investigated the
growth of III-V nanowires, obtained by metallorganic vapor-phase-epitaxy MOVPE at lowtemperatur
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