Layered poly/Amorphous Silicon Deposition Process for Improved Silicide Integrity
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LAYERED POLY/AMORPHOUS SILICON DEPOSITION PROCESS FOR IMPROVED SILICIDE INTEGRITY P. K. Roy, A. K. Nanda, and J. A. Taylor
AT&T Bell Laboratories, 555 Union Boulevard, Allentown, PA 18103
ABSTRACT This work describes an elegant way to control silicide integrity and the quality of the silicide/polySi or amorphous (a) Si interface by a multilayered deposition process. Structurally superior polySi/oa-Si layer resulting from this process allows one to reduce the stack height of the polySi layer without compromising silicide integrity and silicide/Si interfacial qualities. Impact of layering during polySi/a-Si deposition on the silicided structure were evaluated from XRD, RBS, cross-sectional TEM, sheet resistance, and SIMS analysis. INTRODUCTION
The self-aligned TiSi 2 process for submicron CMOS technology has been reported extensively in recent years.1" 2 These silicides have relatively high conductivity, and when lithographically patterned, can serve as gate electrodes for field effect transistors and conductor patterns for interconnects.
Control of silicide integrity and the quality of TiSi 2/polySi or amorphous (ca) Si interface has been the biggest challenge in CMOS process. Ti/polySi or ae-Si thin film reactions have generated interest for both material scientists and process technologists, because the TiSi 2 quality, to 3 a great extent, depends on the substructure and morphology of polySi or a-Si layer. This work describes various studies (XRD, RBS, sheet resistance, SIMS, and TEM) to characterize TiSi 2 layer on polySi and a-Si film at different stages of silicide processing. Impact of layering 4 on these polySi or ca-Si films on phase stabilities6 (C49 and C54) of TiSi 2 films and TiSi 2 / polySi or c-Si interfacial structure are also investigated. EXPERIMENTAL
I PolySi/a-Si DEPOSITION PROCESS Polysilicon films were deposited by silane (SiH 4 ) pyrolysis in a modified five-zone Bruce LPCVD furnace.
4
SiH 4 was introduced at 3 injection ports to compensate the SiH 4
depletion effects while a constant partial pressure across the 125 mm wafers was maintained. Flow rate of the reactant gases were controlled with calibrated mass flow controllers. The deposition pressure was controlled by a MKS type pressure gauge and was regulated by a butterfly valve. The system was then evacuated with a rotary pump and Root's blower, fitted with a water cooled trap. Structural layering for controlling the polySi/ai-Si substructure was attained by a ueriodic fluctuation in deposition rates (D ). For polySi, the rate was varied from 40 A/min to 100 A/min by increasing the CVD pressure from 0.20 to 0.28 torr and SiH 4 flow rate from 22 to 80 sccm at 620'C. For a-Si, deposition rates of 15 and 30 A/min from SiH 4 pyrolysis (550'C at 0.28 to 0.5 torr CVD pressure) was used to achieve layering. Conventional single layer polySi/a-Si films were deposited from SiH 4 pyrolysis at 620 C (0.28 torr) and 550 C (0.5 torr) respectively.
Mat. Res. Soc. Symp. Proc. Vol. 283. 01993 Materials Research Society
648
II PROCESS DESCRIPTION
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