A Self-Aligned Silicide Process Utilizing Ion Implants for Reduced Silicon Consumption and Control of the Silicide Forma
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A SELF-ALIGNED SILICIDE PROCESS UTILIZING ION IMPLANTS FOR REDUCED SILICON CONSUMPTION AND CONTROL OF THE SILICIDE FORMATION TEMPERATURE G. M. Cohen, C. Cabral, Jr., C. Lavoie, P. M. Solomon, K.W. Guarini, K.K. Chan, and R.A. Roy IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 Abstract: We propose a modified self-aligned silicide (salicide) process that uses Ge implantation and a silicon cap to reduce the silicon substrate consumption by 75% as compared with a conventional salicide process. We have used Ge implants to increase the cobalt disilicide formation temperature. This forces the cobalt to react primarily with a deposited silicon cap, thus minimizing consumption from the silicon substrate. We expect this process to be useful for making silicide on shallow junctions and thin SOI films, where silicon consumption is constrained. Introduction: Self-aligned silicide (salicide) is an integral process in the fabrication of high-performance CMOS devices. The salicide process converts the surface portions of the source, drain, and gate silicon regions into a silicide. Due to the low sheet resistance of the silicide film, the series resistance to the intrinsic device is minimized. In bulk devices the silicide film must be contained within the source and drain junction or otherwise it would form a leakage path to the substrate. Moreover, to obtain a good ohmic contact it is desirable to target the silicide/silicon junction to coincide with the peak concentration of the source/drain doping. Scaling the gate length of a MOSFET requires shallow junctions to suppress short channel effects (SCE) [1,2]. The junction depth is expected to become comparable or even thinner than the required silicide film thickness. Meeting the shallow junction requirement and maintaining a thick enough silicide film requires a revision of the conventional salicide process. Scaling of the silicon-on-insulator (SOI) MOSFET leads to similar constraints on the salicide process. In the case of SOI, reducing the channel thickness (tsi) has been found to suppress SCE for both single-gate and double-gate MOSFETs [1]. The use of the conventional salicide process with devices having a very thin SOI channel leads to the following problem: There may not be enough silicon in the source/drain regions to complete the silicide formation. However, even consumption of more than 80% of the silicon film would actually increase the series resistance due to a reduction in the contact area [3]. Constraints on the silicon consumption by silicide imposed by future bulk and SOI technologies require altering the conventional salicide process to be compatible with ultra shallow junction technology and ultra thin SOI films. In a recent publication [4] we discussed a self-aligned silicide (salicide) process that uses a silicon cap to reduce the substrate silicon consumption by 50% as compared with a conventional salicide process. In this paper we propose a modification to the referenced salicide process which uses Ge implants, a cobalt-silicon mixture and a sili
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