Leakage Current and Reliability on Planar High-k Capacitor with Al 2 O 3 Dielectric Deposited by Thermal-ALD
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II.
METHOD AND EXPERIMENT DETAILS
Two planar capacitors configurations are studied: MOS (Metal/Oxide/Semiconductor) and MIM (Metal/Insulator/Metal) capacitors, both containing a 0.54 mm² top aluminum plate. A 50nm-thick-Al2O3 dielectric is deposited on a p-Si high resistivity substrate having a boron concentration of 1.5 1015 – 1.5 1016 atoms/cm3. The MIM structure integrates a 10 nm thick TiN barrier layer on both sides of the Al2O3. The Al2O3 dielectric and TiN are deposited below 400°C by thermal ALD. In the MIM case, TiN precursors are TiCl4 and NH3. Al2O3 precursors are trimethyl aluminum and ozone. These two planar capacitors are used to investigate 50nm-thickAl2O3 dielectric and reliability characteristics when subjected to electrical stresses. Voltage ramp (VRamp), capacitance-voltage (C-V) and time-Dependent dielectric breakdown (TDDB) were carried out. Experimental setup for VRamp and TDDB experiments are in agreement with JEDEC SP001 specification. The MOS device is used for the quantitative determination of the dielectric characteristics: i.e. dielectric bulk defects and conduction mode. The density of bulk defects is calculated back from C-V measurements, through the determination of the flatband voltage [3]. The determination of the conduction mechanisms at high field is based on I(V) linearization and fit with classical Poole-Frenkel model. The dielectric strength evaluation is performed using a VRamp experiment considering the breakdown voltage as figure of merit. TDDB tests in MIM capacitors are presented in the section III.c. Large intra-wafer dispersion is observed and will be discussed with respect to Weibull formalism. III.
EXPERIMENTAL RESULTS
III.a Breakdown field dependency to oxide trapped defect At room temperature, fixed charges (Qfox) are estimated from C-V measurements. The relation between Qfox and the flatland voltage is given by the formula (1) [3]: (1) with -0.95V) the work function difference between metal and semiconductor and oxide capacitance.
the
The distribution of traps density over randomly selected samples on one wafer is presented on the Fig.1. Considering the limited hysteresis observed on the C-V at onset of depletion, it is considered that state of interface is marginal and that Qfox corresponds mainly to fixed charge in the dielectric bulk. Two overlapped distributions are visible on the Kernel Density Estimation (KDE) and can be highlighted from the Cumulative Distribution Function (CDF) above |Qfox|~ 6.7 10-12 at/cm-² out of the Fig.1a. Both are corresponding to different wafer area and the corresponding spatial distribution is presented on the Fig.1b.
(b)
(a)
Figure 1 : (a) KDE and CDF (b) wafer map of charge density across the MOS wafer
A higher trap density is visible (surrounded area on the Fig.1b) compared to the upper edge. A similar wafer signature is also observed on trap energy depth T with shallower traps on the wafer edge (not shown here). The method to calculate the trap energy depth will be presented in the section III.b. The average trap den
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