Gate Stack Reliability of high-Mobility 4 H -SiC Lateral MOSFETs with Deposited AI 2 O 3 Gate Dielectric
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1195-B04-03
Gate Stack Reliability of high-Mobility 4H-SiC Lateral MOSFETs with Deposited Al2O3 Gate Dielectric Daniel J. Lichtenwalner,1 Veena Misra,2 Sarit Dhar,3 Sei-Hyung Ryu,3 and Anant Agarwal3 1
Department of Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-7920. 2 Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695-7920. 3 Power R&D, CREE, Inc., Research Triangle Park, NC 27709.
ABSTRACT Lateral nMOSFETs have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. A bi-layer dielectric was utilized consisting of thin nitrided SiO2 covered by 25nm of Al2O3 deposited using atomic layer deposition. Fieldeffect mobility and threshold voltage (VT) were found to vary with SiC nitric oxide (NO) anneal temperature. High peak mobility values of 106 cm2/V·s were obtained, with a corresponding VT of 0.8 V, using an 1175 °C 20 min NO anneal of the SiC before Al2O3 deposition. Constant voltage stressing (CVS) of the gate (3 MV/cm) for 1000s induces a VT increase of only 0.12 V for the devices stressed at RT, whereas a VT shift of 0.34 V occurs for devices stressed at 150 °C. Heating unstressed devices to 200 °C reveals a stable VT with temperature. Negative charge in the gate region allows for the attainment of positive VT, while VT stability does not suffer.
INTRODUCTION Silicon Carbide has become an increasingly important electronic material, especially in the area of power electronics. However, high interface state densities (Dit) have limited channel mobility in gate-controlled devices such as MOSFETs. Presently, thermal oxidation of SiC to form SiO2 is the process of choice for gate dielectric formation. However, this has typically also resulted in an interface with high Dit levels, due to a variety of defect types, with C-related impurities at the interface being a major issue [1]. Thus there is reason to believe that minimizing SiC oxidation could lead to better quality interface properties [2]. Although annealing thermally grown SiO2 in nitric oxide (NO) results in the increase of mobility [3], device threshold voltage (VT) typically becomes negative as peak mobility increases above about 30 cm2/V·s [4]. Another important gate property related to interface states is VT stability with applied field, shown to be strongly dependent on gate processing [5]. There are a number of reports of the growth of alternative dielectrics on SiC, such as AlN [6] and Al2O3 [7]. It is reported that Al2O3 on SiC can have Dit levels similar to that of thermally oxidized SiC [8]. Additionally, some reports in literature claim
extremely high mobility values (300 cm2/V·s) and positive VT with deposited dielectrics [9], pushing the search towards alternative gate stack fabrication approaches. Threshold voltage control is also a current issue for Si-based MOSFET scaling. It has been demonstrated that the proper choice of gate materials, and their position within the gate (within dielectric, or at top or bottom dielectri
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