Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation
- PDF / 2,075,630 Bytes
- 16 Pages / 595.224 x 790.955 pts Page_size
- 25 Downloads / 190 Views
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation Qiuling Zhu · Christian R. Berger · Eric L. Turner · Larry Pileggi · Franz Franchetti
Received: 22 June 2012 / Revised: 8 November 2012 / Accepted: 20 November 2012 / Published online: 21 December 2012 © Springer Science+Business Media New York 2012
Abstract In this paper we present a local interpolationbased variant of the well-known polar format algorithm used for synthetic aperture radar (SAR) image formation. We develop the algorithm to match the capabilities of the application-specific logic-in-memory processing paradigm, which off-loads lightweight computation directly into the SRAM and DRAM. Our proposed algorithm performs filtering, an image perspective transformation, and a local 2D interpolation, and supports partial and low-resolution reconstruction. We implement our customized SAR grid interpolation logic-in-memory hardware in advanced 14 nm silicon technology. Our high-level design tools allow to instantiate various optimized design choices to fit image processing and hardware needs of application designers. Our simulation results show that the logic-in-memory approach has the potential to enable substantial improvements in energy efficiency without sacrificing image quality. Keywords Synthetic aperture radar · Interpolation · Logic in memory · Chip generator
Q. Zhu () · L. Pileggi · F. Franchetti Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA e-mail: [email protected] C. R. Berger Wireless System R&D, Marvell Semiconductor, Santa Clara, CA, USA E. L. Turner Department of Electrical Engineering and Computer Science, University of California Berkeley, Berkeley, CA, USA
1 Introduction The polar format algorithm (PFA) used for image formation in synthetic aperture radar (SAR) is computationally demanding and data-intensive [1, 2]. Its realtime constraints and low-power requirements make it a promising target for advanced power-saving designs. On the other hand, its overall system performance is often defined by the limited memory bandwidth as well as the high cost of memory access. As a potential solution to address these challenges, the application-specific logic-in-memory (LiM) computing paradigm and its design methodology [3, 4] is proposed to move simple computation directly into the memory, and minimize the data movement from memory to the processors for superior energy efficiency (see Fig. 1). This idea stems from recent studies of sub-20 nm CMOS design, which indicate that memory and logic circuits can be implemented together using a small set of wellcharacterized pattern constructs [5, 6]. Our early silicon experiments in a commercial 14 nm SOI CMOS process demonstrate that this construct-based design enables logic and memory bitcells to be placed in a much closer proximity to each other without yield or hotspots pattern concerns. While such patterning appears to be more restrictive to accommodate the physical realities of 14 nm CMOS, the
Data Loading...
