Electronic Design Automation for Implementation of 3D Integrated Systems
The technology of vertical integration using Through Silicon Vias (TSVs) now is mature for commercial products with a smaller form factor, better performance, less power consumption and lower cost. This paper addresses two challenges faced with the design
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Abstract The technology of vertical integration using Through Silicon Vias (TSVs) now is mature for commercial products with a smaller form factor, better performance, less power consumption and lower cost. This paper addresses two challenges faced with the design using vertical integration. First, methods for the characterization of the physical behavior of the new interconnect structures are described. Second, since issues of reliability and thermal management become more important and difficult and the design space is drastically larger, new early stage design tools are needed. A new floorplanning flow is introduced which supports the cost and performance optimized implementation of digital systems in a stack.
1 Introduction After several years of research, the technologies for 3-D integration of electronic systems are ready for commercial applications. They enable the dense integration of different dies (e.g. analog, CMOS, sensors) in a single package. First 3-D products were image sensors integrated with high performance processors [1]. Today products are mainly based on the reuse of existing designs. Interposers provide the redistribution of signals and interconnections between individual dies of a stack as shown in Fig. 1. This is sometimes called 2.5D design. Through silicon vias (TSV) enable full 3-D-integration by direct interconnection between dies without interposers. This offers a variety of possibilities for new system concepts: • higher performance, due to reduced interconnect length, • lower power consumption by using dedicated silicon technologies for each subsystem, Uwe Knoechel (B) Fraunhofer IIS/EAS, Zeunerstraße 38, 01069 Dresden, Germany [email protected]
A. Heuberger, Microelectronic Systems. DOI 10.1007/978-3-642-23070-7_3, © Springer 2011
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Fig. 1 Interposer based integration of image sensor and processor [1]
• reduction of manufacturing costs for large SoC or multi-processor setups [2], whereat the yield is reduced with increasing die size • and small form factors for applications in smart systems technology [3]. Assuming, that the design starts from scratch, the design space is large. Options are e.g. the number of dies and their individual silicon technologies; interconnect technologies and the order of dies in stack; and the partitioning and placement of functional blocks. Any choice of these options has an impact on performance, yield, reliability, testability, and production costs of a product. Design tools made for 2-D support the design of the individual dies but cannot handle problems of stacking, such as electrical behavior of through silicon vias, heat transfer in a stack, or electromagnetic coupling between different layers. Therefore, 3-D design demands new EDA solutions that support detailed analyses on physical level and provide a modeling strategy how to consider those effects on system level (see Sect. 2). Based on knowledge and models of the multi-physical dependencies in a stack, a cost and thermal aware 3-D floorplanning al
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