Long Time-Constant Trap Effects in Nitride Heterostructure Field Effect Transistors
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Long Time-Constant Trap Effects in Nitride Heterostructure Field Effect Transistors Xiaozhong Dang1, Peter M. Asbeck1, Edward T. Yu1, Karim S. Boutros2,a, Joan M. Redwing2,b Department of Electrical and Computer Engineering, University of California at San Diego, 9500 Gilman Drive, La Jolla, CA 92093-0407 2 Epitronics/ATMI, 21002 north 19th Avenue, Suite 5, Phoenix, Arizona 85027-2726 a Currently: Spectrolabs, 12500 Gladstone Ave., Sylmar, CA 91343 b Currently: Department of Materials Science and Engineering, Pennsylvania State University, University Park, PA 16802 1
ABSTRACT Current collapse effects in an Al0.25Ga0.75N/GaN HFET have been investigated under pulsed bias conditions, and a detailed investigation of current responses to changes in drain or gate bias voltage (drain-lag and gate-lag, respectively) has been performed. Three components of transient current response to changes in drain and gate bias voltages are distinguished. Surface treatment using KOH etching and the influence of pulsed bias conditions on threshold voltage are investigated to explore the origins of traps associated with each current transient component. INTRODUCTION
AlGaN/GaN heterostructure field-effect transistors (HFET’s) have attracted intense research interest due to their outstanding potential for operation at high power, high temperature, and high frequency [1-4]. Despite the attainment of extremely high power densities and total power at microwave frequencies, the microwave power densities reported are often lower than those that would be expected based on measured direct-current (dc) current-voltage (I-V) characteristics [3,4]. Reductions in current flow, i.e. current collapse, and power have also been observed under pulsed bias conditions in GaN field-effect transistors (FET’s) and high-electron-mobility transistors (HEMT’s), and were attributed to traps in these devices [5,6]. A detailed assessment of these effects and characterization of the relevant trap states is crucial for optimization of nitride transistor performance. EXPERIMENT
The HFET structure employed in this study was grown on a c-plane (0001) sapphire substrate by low-pressure metalorganic vapor phase epitaxy, and consisted of a 300 Å nominally undoped Al0.25Ga0.75N barrier layer grown on a 3 µm undoped highly resistive GaN layer. A twodimensional electron gas (2DEG) is formed at the Al0.25Ga0.75N/GaN interface due to the presence of polarization charges [7] and background doping in the Al0.25Ga0.75N layer. Transistors were fabricated using Ti/Al to form the source and drain Ohmic contacts and Ni/Au to form the gate Schottky contact. In these devices, the gate length is 1 µm, the gate width is 25 or 50 µm, the source-drain spacing is 3 µm, and the gate-drain spacing is approximately 1 µm. A more detailed description of the fabrication and dc characterization of these devices can be found elsewhere [8]. I-V characteristics of these devices were measured under both dc and pulsed bias conditions. Significant current collapse effects were observed under both pulsed
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