Low-Power Design and Power-Aware Verification
Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. T
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Low-Power Design and Power-Aware Verification
Low-Power Design and Power-Aware Verification
Progyna Khondkar
Low-Power Design and Power-Aware Verification
Progyna Khondkar Design Verification Specialist Mentor Graphics - A Siemens Business Fremont, CA, USA
ISBN 978-3-319-66618-1 ISBN 978-3-319-66619-8 (eBook) DOI 10.1007/978-3-319-66619-8 Library of Congress Control Number: 2017951845 © Springer International Publishing AG 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
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This Book is Dedicated to My and all Families of the World-
Preface
Low-power (LP) design, power-aware (PA) verification, and Unified Power Format (UPF) or IEEE-1801 power standards are no longer special features. These technologies and methodologies are now part of standard design, verification, and implementation flows (DVIFs). Almost every chip design today incorporates some kind of low-power technique through power management on chip–by dividing the design into different voltage areas and controlling the voltages, through UPF and testbench. Then, the PA dynamic and PA static verification or their combination comes into the play. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the register transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progressi
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