Low-Power Embedded DSP Core for Communication Systems
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Low-Power Embedded DSP Core for Communication Systems Ya-Lan Tsao Department of Electrical Engineering, National Central University, 300 Jung-Da Road, Jung-Li City, Taoyuan 320, Taiwan Email: [email protected]
Wei-Hao Chen Department of Electrical Engineering, National Central University, 300 Jung-Da Road, Jung-Li City, Taoyuan 320, Taiwan Email: [email protected]
Ming Hsuan Tan Department of Electrical Engineering, National Central University, 300 Jung-Da Road, Jung-Li City, Taoyuan 320, Taiwan Email: [email protected]
Maw-Ching Lin Department of Electrical Engineering, National Central University, 300 Jung-Da Road, Jung-Li City, Taoyuan 320, Taiwan Email: [email protected]
Shyh-Jye Jou Department of Electrical Engineering, National Central University, 300 Jung-Da Road, Jung-Li City, Taoyuan 320, Taiwan Email: [email protected] Received 2 February 2003 and in revised form 14 July 2003 This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 µm SPQM and 0.25 µm 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a 16 × 16 version is 100 MHz (0.35 µm) and 140 MHz (0.25 µm). Keywords and phrases: digital signal processor, embedded system, dual MAC, subword multiplier.
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INTRODUCTION
During the past few years, digital signal processor (DSP) has become the fastest growing segment in the processor industry [1]. Today, almost all wireless handsets and base stations are DSP-based systems. Not only technological trends make DSP cheaper and more powerful, but DSP-based systems are also more cost effective and have shorter time to market than other systems [2]. Some DSPs can achieve high throughput by exploiting parallelism with specialized data paths at moderate clock fre-
quency. For example, very long instruction word (VLIW) and single instruction multiple data (SIMD) approaches can be used to further enhance processor performance [3]. However, these approaches are not economical for dedicated application in area and power terms. Consequently, these structures are not suitable for embedded communication applications, in which small area and low-power consumption are critical factors. Instead, an applicationspecific concept is used while maintaining a focus on the targeted application of the
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