Low-Power High-Performance Adders
The scaling of the CMOS channel length to below 0.5 um and increasing of the chip density to the ULSI range have placed power dissipation on an equal footing with the performance as a figure of merit in digital circuit design. Portability and reliability
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2.1 INTRODUCTION The scaling of the CMOS channel length to below 0.5 p,m and increasing of the chip density to the ULSI range have placed power dissipation on an equal footing with the performance as a figure of merit in digital circuit design. Portability and reliability [1] have also played a major role in the emergence of lowpower, low-voltage, digital circuit designs. The need to extend the battery life, to have inexpensive packaging and cooling systems, and to reduce the weight and size of the equipment were the driving forces in this regard. Reducing the power dissipation of arithmetic operations while keeping the performance unaffected, is indispensable for digital signal processing (DSP) ,reduced instruction set computers (RISCs), microprocessors, etc. As an example, high-speed low-power adders are essential as arithmetic blocks. This Chapter explores the circuit and architecture techniques for a 32-bit adder macro targeting low-voltagejlow-power applications. The proposed adder is based on the Conditional Sum Addition (CSA) algorithm [2] combined with Carry Select (CS) . The main contribution is in realizing the CSA adder using a low-power Complementary Pass-Transistor Logic (CPL-like) circuit style. It will be shown that this implementation is better than its TG style counterpart
[3].
The performance of this adder is compared to different 32-bit adders implemented in 0.8 p,m CMOS(in BiCMOS) technology in the range of 3.3 to 1.5 V, using different architectures (Le. Carry Look Ahead (CLA), CS, manchester) with different circuit styles (i.e. conventional static CMOS, Transmission Gate
7 M. S. Elrabaa et al., Advanced Low-Power Digital Circuit Techniques © Springer Science+Business Media New York 1997
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(TG) , CPL [4], and Double Pass-transistor Logic (DPL) [5]). Unlike other comparisons [6, 7], this work explores the minimum size transistor design and then optimizes the delay of th e critical path, and hence keeps the power dissipation low. Thus, two sets of comparisons among all 32-b adder architectures are pr esent ed . The first is for a minimum transistor size design and th e second is for optimized circuit performance. In Section 2.2 the CSA architecture is described along with the critical path delay analysis. The circuit implem entation of the CSA adder is discussed in Section 2.3. Section 2.4 pr esents th e effect of block sizes and staging on the performance of the CSA adder. Sections 2.5 and 2.6 discuss the simulation st rate gy and the performance comparison of the CSA adder to other adder architectures, respectively. The layout strategy is pr esented in Section 2.7 and that is followed by concluding remarks in Section 2.8.
2.2 ARCIDTECTURE A 4-bit block diagram of th e Conditional Sum Adder (CSA) is shown in Figure 2.1 (a). The adder is com posed of conditional sum cells, and a blo ck of 2 to 1 multiplexers (MUXs). Figure 2.1 (b ) shows the gate level implementation of t he conditional sum cell, where SOand COare the sum and carry corr esponding to a carry in of " 0", and SI a
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