Copper Metallization Technology for Deep Submicron ULSIs
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ing length. This means more levels of wiring than what we have at present will be required to develop large-scale integration. The wiring width decreases with decreasing wiring pitch, and wiring resistance becomes significant. Decreased wiring pitch
results in an increase in the wire's parasitic capacitance. There is a limit to how small the space between wires can be; therefore, it is important to lower the permittivity of interlayer insulators such as inorganic 3 SixOyF films and other organic materials. The wiring generally has parasitic resistance and capacitance. When the wiring is wide enough, the wiring resistance is smaller than device resistance, so wiring resistance can be ignored. The wiring can be considered to have capacitance with concentrated constant. On the other hand, when the wiring width is narrow, wiring resistance cannot be ignored. We must consider the distribution constant circuit for resistance and capacitance. The relationship between via resistivity and wiring width is shown in Figure 1. Here, the wiring resistance is equal to the via resistance. When the via contact diameter becomes small, the reduction in via resistance becomes significant. One example of the effect of via resistance on the wiring delay is shown in Figure 2t The ratio of via delay in wiring delay becomes large when the via diameter is about 0.1 /am. The dependence of the via contact resistivity on the sum of the via and wiring
Cu,0.1Via Cu,0.2Via Cu,0.3Via Cu,0.4Via Cu,0.5Via Cu,0.7Via Cu,1.0Via
0.4 0.6 Cu Wiring Width (urn) Figure 1. Dependence of copper via resistivity on copper wiring width with the wiring resistance equal to the via resistance. Via number: 101mm.
MRS BULLETIN/AUGUST 1994
Copper Metallization Technology for Deep Submicron ULSIs
LSIs is dominated by wiring resistance and capacitance. An increase in operation current density and a decrease in resistance and capacitance results in high-speed LSI operation; therefore, the resultant effect of large allowable operation current density and the low resistance on the signal propagation speed of copper wiring is larger than for Al alloys.
a
0.1
0.3
0.5
Cu CVD Technology Copper chemical vapor deposition (CVD) relies on a heterogeneous surface reaction and provides a far better way to cover steps and fill via holes and trenches with high aspect ratios than does conventional physical vapor deposition (PVD). Cu CVD is therefore a natural choice as a technology that can endure several generations of deep submicron miniaturization, low resistance of high-aspect-ratio via holes, high-yield metal filling of via holes and trenches at low temperatures. On the other hand, PVD with conventional high-rate sputtering is a fine way of forming a copper film on a flat surface.
Via Hole Size (urn) Figure 2. Dependence of the sum of wiring and via delay time on via hole size. Wiring length: 20 mm; via resistivity: 1 x 10~g ohm cm2; via number: 101mm.
resistance is shown in Figure 3. The difference in material resistance becomes clear when via resistivity is bel
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