Low Schottky Barrier on N-Type Si for N-Channel Schottky Source/Drain MOSFETs
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Low Schottky Barrier on N-Type Si for N-Channel Schottky Source/Drain MOSFETs Meng Tao, Darshak Udeshi, Shruddha Agarwal, Nasir Basit, Eduardo Maldonado, and Wiley P. Kirk NanoFAB Center and Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX 76019, U.S.A. [email protected] ABSTRACT Schottky source/drain (S/D) in Si-CMOS provide an alternative to current approaches in S/D, channel, and gate-stack engineering. The Schottky S/D PMOS has been demonstrated at a number of university and industrial laboratories. The bottleneck for the Schottky S/D NMOS is the fact that none of the common metals or metal silicides has a low enough barrier height (~0.2 eV) on n-type Si. A method to produce low Schottky barriers on n-type Si with common metals including aluminum (Al) and chromium (Cr) is reported in this paper. The interface between metal and Si(100) is engineered at the atomic scale with a monolayer of selenium (Se) to reduce the density of interface states, and the engineered interface shows inertness to chemical and electronic processes at the interface. One consequence of this electronic inertness is that the Schottky barrier is now more dependent on the metal work function. Al and Cr both have work functions very close to the Si electron affinity. It is found that the Schottky barrier of Al on Seengineered n-type Si(100) is 0.08 eV, and that of Cr is 0.26 eV. These numbers agree well with the ideal Schottky barrier heights for Al and Cr on n-type Si(100), but are significantly different from the barrier heights known for four decades for these metals on n-type Si(100). These results bring new hope for the Schottky S/D NMOS with a metal commonly used in the Si industry. INTRODUCTION Schottky S/D in Si-CMOS [1] provide an alternative to current approaches in S/D, channel, and gate-stack engineering. For example, current efforts in shallow junctions, deposition of heavily-doped S/D, dopant activation, new silicide, and raised S/D are unnecessary with Schottky S/D. The channel doping in Schottky S/D CMOS is much lower than in classical CMOS, which reduces gate depletion and eliminates the need for metal gates. Moreover, Schottky S/D CMOS is a majority-carrier device, instead of a minority-carrier one as classical CMOS. It has a smaller junction RC constant than classical CMOS. These merits provide the potential for Schottky S/D CMOS to outperform p-n junction S/D CMOS. In fact, Schottky diodes have shown performance comparable to tunneling diodes and oscillation diodes with cutoff frequencies well into the terahertz regime. The Schottky S/D PMOS has been demonstrated at a number of university and industrial laboratories [1-5]. The bottleneck for the Schottky S/D NMOS is the fact that none of the common metals or metal silicides has a low enough barrier height (~0.2 eV) on n-type Si. Exotic materials, therefore, have to be used to obtain the right barrier height, such as erbium silicide that is readily oxidized in air [5], or titanium germanide-silicide that introduces many more process
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