Self-Assembly CoSi 2 -Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI
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Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI Patrick Kluth, Qing-Tai Zhao, Stephan Winnerl, and Siegfried Mantl Institut für Schichten und Grenzflächen (ISG-IT), Forschungszentrum Jülich, D-52425 Jülich, Germany ABSTRACT A new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics. INTRODUCTION Scaling of silicon metal oxide semiconductor field effect transistors (MOSFETs) becomes difficult when gate lengths shrink below 100 nm. Lithography techniques increase in complexity and new materials and processes need to be developed to fulfill the stringent requirements that the International Roadmap of Semiconductor Devices (ITRS) [1] imposes on the performance of future silicon devices. This encourages the search for alternative and reasonably priced nanopatterning methods as well as for new device concepts. Self-assembly patterning is one attractive way to produce nanostructures quickly and at a very low cost. Recently, we published a self assembly method for patterning thin epitaxial CoSi2 layers into nanostructures by local oxidation of silicide layers [2,3]. In microelectronics, the silicide CoSi2 has emerged as a leading choice as a contact and interconnect material due to its low resistivity and high scalability. A major challenge associated with downscaling of conventional MOSFETs is the formation of highly doped ultrashallow junctions to maintain low series resistance and avoid short channel effects. Dopant diffusion is difficult to control at nanometer dimensions. As one promising approach to solve these problems, Schottky barrier MOSFETs (SBMOSFETs) have been proposed [4-7]. We have shown that SBMOSFETs can be produced using our nanopatterning method [2]. In this paper we present initial results on SBMOSFETs fabricated on silicon-on-insulator (SOI) substrates using this technique. We will focus on the device fabrication and their dual-
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