Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond
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Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond John O. Borland Varian Semiconductor Equipment Associates 4 Stanley Tucker Dr. Newburyport, MA 01950, USA ABSTRACT Low temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it’s interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000oC) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to
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