Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond
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1249-E01-06
Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond John H Zhang1, Laertis Economikos2, Wei-tsu Tseng2, Jihong Choi3, Qiang Fang3, Teck Jung Tang3, Joe Salfelder4, Connie Truong2 and Paul Ferreira1 1
STMicroelectronics, 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. IBM Semiconductor Research and Development Center (SRDC), 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. 3 GlobalFoundries Inc, 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. 4 Applied Materials, 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. 2
ABSTRACT Studies of the wafer edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using scanning electron microscopy (SEM) measurements, showed that the major wafer non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 (P1) using real time profile control as well as CMP head zone pressure adjustment and platen 3 (P3) slurry optimizations INTRODUCTION As device dimensions continue to shrink at each integrated circuit generation, chip performance becomes increasingly limited by back end of the line (BEOL) process due to interconnect delay (RC). In order to minimize this delay, one of the most important changes is the introduction of a porous dielectric to significantly reduce the dielectric constant. The ultra low-k (ULK) brings a new material for CMP to deal with [1]. In copper planarization the bulk copper is removed first using a high removal rate process, followed by a lower removal copper clearing process and finished with barrier removal process. Each step contributes to the final topography on the wafer. Typically the bulk removal reduces significantly the topography introduced by plating. But some topography remains after the bulk copper removal which depends on the planarization process. An important characteristic of CMP processes is the planarization across the wafer with least dependence on pattern densities compared to other methods. For maximum performance the chip designers require sheet resistances to be close to a specific target with only little variation. A challenge is the increasing number of metallization levels, as topography builds up an inadequate planarization will lead to defects formed in subsequent layers as well as performance mismatch [2, 3] The interconnect levels at the 32nm node and beyond present significant challenges to process integration and to unit processes, including CMP. The problem is a complex interplay between the ability to pattern low k/ULK dielectrics, the ability to fill the resulting trenches with copper, and the requirements for CMP of the copper/liner/hard mask material set. One of the biggest challenges to CMP is to produce a composite copper/dielectric structure which has uniform thickness across varying pattern densities and feature sizes and across the wafer [4]. There are many factors affect the CMP uniformities [5, 6]. In this paper, the edge nonuniformity o
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