MANOS erase performance dependence on nitrogen annealing conditions
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MANOS erase performance dependence on nitrogen annealing conditions Vassilios Ioannou-Sougleridis 1, Nikolaos Nikolaou 1,2, Panagiotis Dimitrakis 1, Pascal Normand 1 , Dimitrios Skarlatos 2, Anastasios Travlos 1, Kaupo Kukli 3,4 ,Jaakko Niinisto 3, Mikko Ritala 3 and Markku Leskela 4 1 Institute of Nanoscience and Nanotechnology, NCSR Demkritos, Athens , Greece 2 Department of Physics, University of Patras, Patras Greece 3 Department of Chemistry, University of Helsinki, Helsinki Finland 4 Institute of Physics, University of Tartu, Tartu Estonia . ABSTRACT In this work we examine the electrical characteristics and the memory properties of metal-alumina-nitride-oxide-silicon (MANOS) devices as a function of the post deposition annealing conditions. Post deposition annealing of the samples was performed at 850 or 1050 oC in nitrogen ambient using two different processes: (1) Furnace annealing for 15 min and (2) rapid thermal annealing for 1 or 5 min. The capacitance equivalent thickness as extracted from the capacitance voltage characteristics depends strongly on the annealing process, being smallest for the furnace annealing. Furthermore, the experimental results indicate that the type of the annealing determines the defect state density of the Al2O3 layer, via which the undesired effect of gate electrode electron injection takes place in the negative voltage regime. For inert ambient annealing the furnace process appears more efficient as compared to RTA. INTRODUCTION The continuation of the non-volatile memory technology downscaling beyond the 20 nm node is based increasingly in charge-trapping (CT) memory devices [1-2]. MANOS has been proposed as an evolution of well-known silicon-oxide-nitride-oxide-silicon (SONOS) where the SiO2 blocking oxide is replaced by an thicker Al2O3 layer and the polysilicon gate electrode is replaced by a metal such as TaN [3]. One of the primary methods for the deposition of the Al2O3 layer is by the atomic layer deposition (ALD) [4] which provides an amorphous layer with a gap of 6.2 eV and a permittivity value within the range of 7-11 [5]. These properties fulfill the requirements for the use of the alumina as a blocking dielectric in CT memory applications. It is evident that the quality of the Al2O3 layer has a profound impact on the properties of the MANOS stacks since it controls the current from and to the gate electrode. It has been shown that the ALD Al2O3 layer in the as-deposited state has a high defect density which gives rise to strong leakage current in the negative gate voltage regime due to electron injection from the gate electrode [6-7]. This electron leakage current constitutes a significant reliability issue for the MANOS memory stack and inhibits the functionality of the MANOS as a memory element [8]. A post deposition annealing step (PDA) step at high temperatures is considered therefore necessary to improve the quality of the Al2O3 [9]. In this work we examine the properties of MANOS capacitors which had undergone either rapid thermal annealing (RTA) or furnace
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