Design for Manufacturability and Yield for Nano-Scale CMOS
As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materi
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Series on Integrated Circuits and Systems Series Editor:
Anantha Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts
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DESIGN FOR MANUFACTURABILITY AND YIELD FOR NANO-SCALE CMOS
by
CHARLES C. CHIANG Synopsys Inc. Mountain View, CA, USA and
JAMIL KAWA Synopsys Inc. Mountain View, CA, USA
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4020-5187-6 (HB) ISBN 978-1-4020-5188-3 (e-book) Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands. www.springer.com
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To my wife Susan (Show-Hsing) and my daughters Wei Diana and Ann - Charles
To my wife Zeina and my children Nura,
