Materials Aspects to Consider in the Fabrication of Through-Silicon Vias
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0970-Y06-01
Materials Aspects to Consider in the Fabrication of Through-Silicon Vias S. Burkett1, L. Schaper1, T. Rowbotham1, J. Patel1, T. Lam1, I. U. Abhulimen1, D. D. Boyt2, M. Gordon2, and L. Cai1 1 Electrical Engineering, University of Arkansas, Fayetteville, AR, 72701 2 Mechanical Engineering, University of Arkansas, Fayetteville, AR, 72701
ABSTRACT The formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 µm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325ºC. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. This paper presents materials aspects to consider when fabricating through silicon vias (TSVs). Modeling of the Cufilled vias to investigate thermal management schemes and Cu posts to investigate mechanical reliability is also presented. I. INTRODUCTION Research activity in the area of 3D interconnects to stack die or wafers has dramatically increased in the past few years. Several research organizations, companies, and university laboratories are developing a variety of approaches and techniques to realize this technology in devices and systems. According to the International Technology Roadmap for Semiconductors (ITRS), 3D interconnection was identified as a “top technical challenge” for 20051 although to date there is not a roadmap for through-silicon vias2. The technology has the ability to reduce delay time and power use due to shortened interconnect lengths as well as to reduce space by using the vertical dimension. Micron Technology, in Boise, Idaho, has an innovative chip packaging technology (Osmium) that incorporates interconnects directly under the bond pads, therefore eliminating the need for wire bonding and enables die stacking.3 RTI International and DRS Infrared Technologies are collab
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