Mechanistic Study of the Deposition of Metals from HF Solutions onto Silicon Wafers
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H.G. PARKS*, J.B. HISKEYt, and K. YONESHIGE* * Electrical and Computer Engineering Department, The University of Arizona, Tucson, AZ 85721 t Materials Science and Engineering Department, The University of Arizona, Tucson, AZ 85721
ABSTRACT Process chemicals in use today are quite pure, depending on the grade used but can easily be contaminated with metal ions through improper handling or storage techniques. Such metal impurities, if deposited on wafer surfaces during processing can increase reverse-bias junction leakage, degrade oxide breakdown strength and increase metal oxide semiconductor capacitor leakage which in turn can adversely affect the function of ultra large scale integrated (ULSI) circuits. Because of these device effects and since metal contamination can come from several sources it is important to know the deposition level and mechanism on Si wafers from a given process solution. HF based process solution have been investigated due to their historical use in patterning, etching, and their increased use in advanced wafer cleaning processes. Multi-contaminant experiments have been designed to study the probability of, and mechanism for deposition. It is shown that in general single element deposition is predicted by electrochemical considerations based on redox reactions, however, potential complex synergistic interactions can cause deviations from the simple theory. Specifically, Sn is shown to inhibit the deposition of Ag, and Mo does not deposit in proportion to the amount of Mo in solution, but does deposit on wafers in the presence of Cu and/or Ag. Detailed analysis of Cu and Ag from BOE and Cu from HF shows the deposition: is statistically uniform over bare Si wafers, is independent of substrate doping and rinse time, does not occur on SiO 2 , is linear with time (up to 25 min) and solution concentration ( up to 500 ppb), shows an Arrhenius behavior with temperature (15 - 55"C) and increases surface micro-roughness. Interpretation of these results with an Evans diagram indicates the deposition is mass transport limited, allowing a first order quantitative theoretical interpretation of the deposition process.
INTRODUCTION It is well known that presence of metal ions can degrade the electrical performance of solid state devices. Metal impurities can create generation-recombination centers in silicon that increase reverse-bias junction leakage [1]. These impurities also affect oxide breakdown strength and metal-oxide-semiconductor (MOS) capacitor leakage by dislocation decoration and stacking fault formation [2,3]. Degradation of device performance can adversely affect the function of ultra large 245 Mat. Res. Soc. Symp. Proc. Vol. 318. ©1994 Materials Research Society
scale integrated (ULSI) circuits, particularly the refresh characteristics of advanced dynamic RAM cells [4]. Sources of trace metal contaminants include the process equipment, process materials, and even process chemicals used in wafer cleaning operations [3]. Process chemicals in use today are quite pure; depending upon the gra
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