Microstructural characterization of copper metallic deposition by electroplating growth for SIP applications
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Microstructural characterization of copper metallic deposition by electroplating growth for SIP applications Céline Durand1, Bernadette Domengès2 and Philippe Le Duc1 1 IPDIA, 2 rue de la Girafe, 14000 Caen , France 2 LAMIPS, CRISMAT – NXP semiconductors laboratory, CNRS-UMR6508, ENSICAEN, UCBN, Presto Engineering Europe, 2 rue de la Girafe, 14000 Caen, France ABSTRACT Microstructural characterization (Focused Ion Beam and Transmission Electron Microscopy imaging) was performed on cross-sections of contacts in thick Electro Chemical Deposition copper metallization of System In Package Integrated Circuits. It was shown that the lower growth rate of ECD-Cu in the AlSiCu – barrier Ti – PVD-Cu – ECD-Cu layer stacking is related to a local higher resistivity induced by the presence of a great number of almost planar grain boundaries in the PVD-Cu layer, which are perpendicular to the growth axis. This morphology is a consequence of the almost heteroepitaxial growth of Ti layer on AlSiCu layer. INTRODUCTION Demands for "System In Package" solutions are growing as they represent one of the most important ways of downsizing Integrated Circuits. The integration of passive components (capacitors, inductors) associated with several micron thick copper metallization required to transfer from metallurgy industry ElectroChemical Deposition (ECD) process. Thus, its optimization based on physical, chemical and microstructural studies pointed out, besides the necessary control of deposition tool and electrolytic bath evolution, the strong influence on the process of the crystallographic structure of the copper under-layers. Based on fine microstuctural characterization, this paper tries to explain why the stacking Al – Ti – PVD-Cu strongly lowers the growth rate of ECD-Cu metallization. EXPERIMENTAL Copper metallization principle The studied samples were processed during optimization stage of copper metallization for SIP applications [1]. The integration of passive components (capacitors, inductors) requires several micron thick copper patterned metallization which can only be achieved using a selective deposition technique such as electroplating. The latter is a process that reduces metal ions electrochemically from an electrolyte where metal ions are dissolved onto a solid conductive surface [2, 3]. Thus a metallic seed layer has to be firstly deposited. The main steps of the ECD process are the following : barrier Ti layer PVD (sputtering), seed Cu layer PVD, photolithography, surface preparation, Cu layer ECD (Technotrans Microform200 system
adapted for our applications), photoresist removal, thermal treatment (ensuring the control of the growth of the copper grain size), surface preparation, seed layer etching, barrier layer etching. Microstructural characterization In a first step, FEI 200XP Focused Ion Beam (FIB) system was used to prepare sitespecific cross-sections and Transmission Electron Microscopy (TEM) lamellae. It is a singlebeam FIB system (30kV Ga+ ion beam and Pt deposition chemistry) adapted to lift-out in situ
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