Modeling of a GaN Based Static Induction Transistor
- PDF / 152,356 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 26 Downloads / 156 Views
Figure 1. Cross-section of static induction transistor (SIT) structure considered in this work and the unit cell simulated with critical dimensions labeled. Electrons are emitted from the source, which is at ground potential, and are accelerated to the drain, which is biased at positive potential, where they are collected [4]. A very thin heavily doped layer is deposited next to the drain and source contacts in order to form ohmic contacts. A grid structure is located in the space between the source and drain electrodes so the charged carriers can be externally modulated. The RF gain of the device is determined by the efficiency
1 Downloaded from https://www.cambridge.org/core. IP address: 83.171.253.18, on 26 Mar 2019 at 11:05:44, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/terms. https://doi.org/10.1557/S1092578300003276
with which the modulation is affected. The grid structure is generally fabricated using pn or Schottky junctions. A range of field effect transistors including MESFET, MISFET, inverted channel AlGaN/GaN and MODFET have been developed with potential applications for high power/ high temperature electronics [2,5-8]. To our knowledge, the highest cut-off frequency reported for GaN-based FET’s is 52 GHz [9], and the maximum frequency of oscillations is over 97 GHz [10]. Significant results regarding the power output of GaN-based FET’s have been reported by several groups [9, 11]. Wu reported an output power of 3 W/mm at 18 GHz, with a power added efficiency (PAE) of 19% for a 0.25 µm gate AlGaN/GaN MODFET [9]. In comparison, our SIT simulation results show a cut-off frequency fT of 24.8 GHz, a maximum frequency of oscillations fmax of 75.2 GHz. Operated under class B, the output power decreases from 10.75 W/mm to 1.95 W/mm as the operating frequency changes from 2 GHz to 40 GHz. Correspondingly, the PAE changes from 73.8% to 9.1 %. THEORY Basic simulation equations and physical models We employed a commercially available 2D device simulator (ATLAS [12]) which was modified appropriately for GaN, based on experimental observations and theoretical calculations. The transistor was modeled with coupled drift-diffusion and heat-flow equations. The effect of lattice temperature on the performance of the device was taken into account by including the thermoelectric factor in current density equations (1,2) and by adding the heat-flow equation (3). J n ( x, y ) = n( x, y )qµ n E ( x, y ) + qDn ∇n( x, y ) − qµ n n( x, y ) Pn ( x, y )∇T ( x, y ) J p ( x, y ) = p ( x, y )qµ p E ( x, y ) − qD p ∇p ( x, y ) − qµ p p( x, y ) Pp ( x, y )∇T ( x, t )
(1) (2)
∂T ( x , y ) = ∇ (κ ∇ T ( x , y )) + H ( x , y ) ∂t (3) where T is the lattice temperature, and Pn and Pp are thermoelectric power coefficients for electrons and holes, respectively, C is the heat capacitance per volume (1.97 J/K cm3 [13]), κ is the thermal conductivity (1.3 W/cm K [14]) and H is the heat generation based on Joule effect. The models used in the simulation are based on those from Si and GaAs, but have
Data Loading...
