Transistor Aging Compact Modeling
The focus of this work is on simulation and analysis of the impact of transistor aging on ICs integrated in nm CMOS processes. Accurate circuit simulation starts with the availability of good transistor compact models. This chapter therefore discusses the
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Transistor Aging Compact Modeling
3.1 Introduction The focus of this work is on simulation and analysis of the impact of transistor aging on ICs integrated in nm CMOS processes. Accurate circuit simulation starts with the availability of good transistor compact models. This chapter therefore discusses the development of a set of models for simulation of the most important aging effects. Most models present in literature focus on understanding the underlying physical effects related to transistor aging, rather than on developing a good compact model. Such a compact model should not only be accurate, but also easy to calibrate and easy to evaluate. Further, it should include all important circuit parameters such as applied stress voltages, transistor dimensions, temperature, etc. This chapter discusses the development of a transistor compact model for the most important transistor aging effects. First, Sect. 3.2 discusses existing models for hot carrier injection and then proposes a new model optimized for analog circuit simulation. Similarly, Sect. 3.3 first focuses on existing models for bias temperature instability (NBTI). These models, however, are typically too complex for circuit simulation or do not properly include the impact of time-varying stress. Therefore, a new NBTI compact model, solving these problems, is proposed. Next, Sect. 3.4 focuses on models for time-dependent dielectric breakdown. Section 3.5 then proposes an aging-equivalent transistor model to enable simulation of the combined impact of all the different aging effects. To enable a designer to do get a quick estimate of the impact of aging on a circuit, Sect. 3.6 also discusses a firstorder aging model for hand calculations. The conclusions of this chapter are given in Sect. 3.7.
E. Maricau and G. Gielen, Analog IC Reliability in Nanometer CMOS, Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-6163-0_3, © Springer Science+Business Media New York 2013
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3 Transistor Aging Compact Modeling
3.2 Hot Carrier Injection Transistor damage due to hot carrier injection (HCI) was a major reliability problem in the early eighties (Takeda et al. 1983; Tam et al. 1984; Hu et al. 1985). Later, when supply voltages were scaled down and graded drain junctions were introduced, HCI became a less dominant reliability problem. However, HCI can still pose a problem for circuits processed in high voltage or older CMOS technologies (i.e. >90 nm) (Moens et al. 2010). Even analog circuits processed in more advanced nodes could be at risk, especially when large voltages are applied (e.g. inductor-based oscillators or power amplifiers) (Chouard et al. 2010; Sagong et al. 2011). Therefore, it is still important to correctly estimate the impact of HCI on the behavior of a circuit. This requires an accurate HCI compact model. HCI mainly occurs in nMOS transistors and causes a shift of important transistor parameters such as the threshold voltage and the carrier mobility. This section first reviews the most important HCI models published in literatur
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