Multilayer Graphene-Based Carbon Interconnect
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Multilayer Graphene-Based Carbon Interconnect Tianhua Yu1,2, Edwin Kim1, Nikhil Jain1, and Bin Yu1 1
College of Nanoscale Science and Engineering, State University of New York at Albany, Albany, NY 12203, U.S.A. 2 Novellus Systems Inc. San Jose, CA 95134, U.S.A. ABSTRACT 3D stacked (or uncorrelated) multilayer graphene (s-MLG) is investigated as a potential material platform for carbon-based on-chip interconnects. S-MLG samples are prepared by repeatedly transferring and stacking the large-area CVD-grown graphene monolayers, followed by wire patterning and oxygen plasma etching of graphene. We observed superior wire conduction of s-MLG over that of monolayer graphene or ABAB-stacked multilayer graphene. Further reduction of s-MLG resistivity is anticipated with increasing number of stacked layers. Electrical stress-induced doping technique is used to engineer the Dirac point, as well as to reduce graphene-to-metal contact resistance, improving the overall performance metrics of the sMLG system. Breakdown experiments show that the current-carrying capacity of s-MLG is significantly enhanced as compared with that of monolayer graphene. INTRODUCTION As the critical physical dimensions of semiconductor integrated circuits continue to be scaled down, the speed performance and reliability of the chip system are increasingly dominated by the metal (copper)-based interconnects [1]. According to the ITRS Roadmap, onchip interconnect wire width and current density will reach 22 nm and 5.8x106 A/cm2 (the maximum capacity in Cu: ~106A/cm2), respectively, by the year 2020 [2]. Thermal dissipation and electromigration (EM)-related failure due to intensified current distribution post additional limits to the ultra-scaled systems [3]. Innovative concepts for the next-generation “post-copper” on-chip interconnect is largely demanded to tackle the challenges in performance, scalability, and reliability. In recent years, low-dimensional carbon nanostructures have been intensively explored for potential interconnect applications due to their superior electrical, thermal, and mechanical properties, as well as the excellent immunity to EM [4-6]. Graphene, a two-dimensional monolayer of sp2-bonded carbon atoms, has been the focus of research recently [7]. Unique properties of graphene have been reported, including ultra-high electrical and thermal conductivities [8,9]. For interconnect design, monolayer graphene nanoribbon (GNR) is expected to outperform Cu at ultra-scaled width dimensions [10]. Although the maximum current-carrying density up to 108 A/cm2 (~100 times of Cu) was reported, performance and scalability of monolayer GNR-based wire is significantly limited by its 2D atomically-thin geometry, sensitivity to ambient, poor noise tolerance, and electrical conductance degradation due to edge-related effects [11,12]. Multilayer graphene (MLG) can potentially be used to lower the interconnect resistance, especially at small wire dimensions where size effects severely limit the conductivity of metal wires. In the case of Bernal stack
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