Stacked Silicon Interconnect (SSI)
A growing trend in the semiconductor market is to gravitate toward 2.5D and 3D technologies as a way to extend and improve the growth and integration path that Moore’s law has paved for more than 50 years. Xilinx has been a forerunner into this emerging t
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Stacked Silicon Interconnect (SSI) Brian Philofsky
A growing trend in the semiconductor market is to gravitate toward 2.5D and 3D technologies as a way to extend and improve the growth and integration path that Moore’s law has paved for more than 50 years. Xilinx has been a forerunner into this emerging technology entering into this foray in 2011 with the public introduction of the Xilinx XC7V2000T device utilizing four active die on a passive interposer creating not only the largest FPGA of the time but one of the first commercially available examples of this new technology. Since the introduction of that device, several other devices have followed and now are becoming a more mainstream means to realize large, high-performance devices to address some of the most demanding FPGA designs. Due to the sheer size and unique construction of these devices, a new approach to design should be considered in order to facilitate design entry, implementation, and closure.
13.1
SSI Terminology
With Xilinx being one of the first companies to release a 2.5D device, no established terminology for the details of the technology existed prior. So as a means to communicate this, several new terms were created by Xilinx to describe the differences in the 2.5D devices. Figure 13.1 shows a representation of SSI device. • Monolithic Device: Single-die or non-SSI device • Super Logic Region (SLR): An active die in an SSI device construction. • Stacked Silicon Interconnect (SSI): The 2.5D structure utilizing multiple active SLRs attached and connected to a passive interposer
B. Philofsky (*) Xilinx, Longmont, CO, USA e-mail: [email protected] © Springer International Publishing Switzerland 2017 S. Churiwala (ed.), Designing with Xilinx® FPGAs, DOI 10.1007/978-3-319-42438-5_13
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Fig. 13.1 Representation of an SSI device (source: Xilinx)
• Interposer: A passive layer in the construction of an SSI device that serves the purpose of power delivery, configuration connectivity, and connectivity between SLRs as well as connects the SLRs to the package substrate via through-silicon vias (TSVs) • Super Long Line (SLL): The active signals used to connect one SLR to an adjacent SLR in an SSI device. • Laguna: The dedicated interface to traverse from one SLR to another via an SLL. This interface may or may not use a dedicated register. The first thing that should be stated is that SSI devices do not require an all new design methodology. It is possible to target an SSI device using the same top-down method generally applied to monolithic devices with no difference in design entry, implementation, and validation. The thing that needs to be realized however is that ignoring the size and construction of the underlying device may lead to less optimal results and a longer design cycle.
13.2
Design Partitioning
One of the first SSI-specific decisions is to either chose to manually select or partition the logic to each underlying SLR in the device or to allow the tools to automatically partition the design into the sepa
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