Nanocrystalline Silicon TFTs With 50 nm Thick Deposited Channel Layer, 10 cm 2 /Vs Electron Mobility and 10 8 On/Off Cur
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Nanocrystalline Silicon TFTs With 50 nm Thick Deposited Channel Layer, 10 cm2/Vs Electron Mobility and 108 On/Off Current Ratio Robert B. Min and Sigurd Wagner Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, USA ABSTRACT Thin film transistors were made using 50 nm thick directly deposited nanocrystalline silicon channel layers. The transistors have coplanar top gate structure. The nanocrystalline silicon was deposited from discharges in silane, hydrogen and silicon tetrafluoride. The transistors combine a high electron field effect mobility of ~ 10 cm2/Vs with a low "off" current of ~ 10-14 A per µm of channel length, and an "on"/"off" current ratio of ~ 108. This result shows that directly deposited silicon can combine high mobility with low "off" currents. INTRODUCTION Integrated backplane circuits are key to the widespread application of large-area electronics, which today comprises liquid crystal displays and X-ray detector arrays, but eventually will extend to sensor skin, mechatronic materials and electrotextiles. These large area backplane circuits will be based on unit cells, or pixels, which contain the basic function and its control, for example, a light emitter switched and powered in a sample-and-hold circuit. Each cell may contain some intelligence used for local signal processing in amplification, addressing and multiplexing. A neighborhood of cells will be controlled by a higher-performance circuit, and the entire backplane will be addressed by driver circuits. Pervasive circuit integration will be needed to make such backplanes affordable. Such integration requires that one single transistor material and process be used for all hierarchical functions, ranging from switching over highspeed signal reception and multiplexing. In other words, the backplane transistor technology should perform similarly to complementary metal-oxide-semiconductor (CMOS) circuits made in single crystal silicon. For this reason we have been pursuing thin film transistor technology based on nanocrystalline silicon, nc-Si:H. This semiconductor can provide high electron mobility [1,2, 3, 4] and sufficient hole mobility to host CMOS circuits [1,2], and it can be made at temperatures that are compatible with the plastic substrates envisaged for roll-to-roll production [4]. However, nc-Si:H is a complex material whose deposition and device processing are not yet mature. The high mobility material develops only over a certain film thickness and then often is coupled with a high transistor leakage current in the OFF state. It is this specific problem that we addressed by fabricating nc-Si:H TFTs with very thin I-layers. Figure 1 is the transfer characteristic of an nc-Si:H n-channel thin film transistor (TFT) [1]. Its "on" current is at least one order of magnitude higher than that of amorphous silicon TFTs of comparable channel width / length ratios. This is a manifestation of high electron mobility. Also note that the "off" current is ~ 10-9 A, a value that lies three orders of magnitude above the
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