Nanoscale Electron-Beam Processes and Its Application to Nanodevices
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advanced research and development. The gate length of MOS transistor for recent LSI is pursuing to be less than 130 nm dimension and 10-nm gate length MOS transistor has been also successfully produced by electron beam lithographic procedures. On the other hand nanometer scale devices such as single-electron transport is expected to be future integrated circuits such as memory and logic, probably, which will be combined with CMOS systems. Thus the lithography technology required for development of advanced LSI and also nanodevices is strongly needed. There have been a lot of reports to produce miniature structures with nanometer dimension such as self-assembled material growth technique and scanning probing methods. However electron beam (EB) lithography is most powerful tool and technique because of its finely focused performance, its flexibility for pattern delineation and rather high writing speed. Resist materials exposed to EB is important to get sharp and smooth line edge and also to transfer patterns with fidelity such as etching and deposition. When the fine line patterns are written on the conventional polymer resist, the edge of the line becomes rough with a standard deviation of about 2-4 nm partly due to instrumentation error which is called nano-edge roughness. Several research groups have investigated the origin of this roughness. The NTT group has revealed that the cause of nano-edge roughness is structure of granular and/or aggregates of resist molecules with about 20-30-nm diameter [13]. They have also showed that the size of aggregates is increased with the increase of molecular weight, so that a resist film with lower molecular weight may indicate smaller roughness. Thus the requirement for nanometer scale lithography is development of high305 Mat. Res. Soc. Symp. Proc. Vol. 584@ 2000 Materials Research Society
resolution resist system in addition to development of fine EB exposure system. In this review article, EB exposure properties of thermally grown SiO2 film and its application of metal liftoff process for producing metal/insulator/metal (MIM) tunnel junctions are described [4-9]. In addition, EB induced direct deposition technique for MIM structures are summarized [10-14], which has advantages of process simplicity, without etching or metal liftoff and of the independent controllability of junction parameters such as capacitance and resistance. In EB-induced deposition, Matsui et al. [15,16] reported that metallic films and 15 nm diameter W rods were produced using electron-stimulated dissociation of adsorbed precursor molecules such as WF 6 and SiH 2C12, although these reports did not measure electrical properties. Koops et al. [17,18] measured the resistivity of 10-2 9cm and 1 fcm deposition using Me 2Au (tfac) and CpPtMe3 gases as precursor molecules and degradation was assumed due to the crystallite structure of the deposit and inclusion of C and 0 from the legand of the precursor molecule and from residual ambient.
2. EXPERIMENT The EB exposure system used here has a sample chamber
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