Nanoscale Transistors: Physics and Materials
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Nanoscale Transistors: Physics and Materials Mark S. Lundstrom, Kurtis D. Cantley, and Himadri S. Pal Network for Computational Nanotechnology, Dept. of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907
ABSTRACT We analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of these hypothetical devices and future generations of devices from the ITRS roadmap, including double-gate MOSFETs. We conclude that a Si channel device with a high-k gate dielectric and metal gate will outperform III-V channel materials for conventional CMOS applications, but will still not suffice in achieving long-term ITRS goals.
INTRODUCTION Much has been accomplished in the way of improving MOSFET device characteristics for continuation of Moore’s law. Strained silicon channels and modified gates and insulators have helped a lot, and the most current 65nm technology produces ~1600µA/µm of drive current with a 1.2V power supply and 1.2nm SiON gate insulator. But this is not enough, and new methods are needed to meet future ITRS roadmap requirements [1]. Options being explored include new device structures such as the tri-gate/finFET and new materials for the gate (FUSI/metal), insulator (high-k dielectrics), and channel (III-V semiconductors). This paper examines the extent to which these new materials options can address the device performance challenges at the end of the ITRS. To predict how a new material or structure will affect performance, it is first necessary to understand the operation of a present-day device. A short review of the theory behind ballistic devices is presented in the next section, as a refresher for those familiar with the concepts, and as a brief but essential introduction for those who are unfamiliar. Topics include calculation of inversion charge, thermal and injection velocities, and ballistic drain current. In the analysis section, a detailed examination of the 65nm device is presented using actual experimental data for the transistor. Important device parameters such as leakage current, subthreshold swing and DIBL are taken directly from the published results, and accurate estimations for threshold voltage and series resistance are made based on both the ITRS roadmap and published measurements. We calculate the ballistic efficiency of the intrinsic device using a comparison of the on currents and of injection velocity. Our analysis supports a similar, recent study on the same device [2], and provides a starting point to examine various device options.
In the discussion section, we use a simple ballistic model to determine the performance of similar MOSFETs, but with different materials. The gate is made into a metal, the insulator a high-k
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