Nanothick Layer Transfer of Hydrogen-Implanted Wafer Using Polysilicon Sacrificial Layer
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0921-T05-02
Nanothick Layer Transfer of Hydrogen-Implanted Wafer Using Polysilicon Sacrificial Layer C. H. Huang1, C. L. Chang1, Y. Y. Yang1, T. Suryasindhu1, W. -C. Liao1, Y. -H. Su1, P. W. Li2, C. -Y. Liu3, C. S. Lai4, J. -H. Ting5, C. S. Chu6, C, -S, Lee7,8, and T. -H. Lee1,8 1
Dept. of Mechanical Engineering, National Central University, Chung-Li, Taiwan
2
Dept. of Electrical Engineering, National Central University, Chung-Li, Taiwan
3
Dept. of Chemical and Materials Engineering, National Central University, Chung-Li, Taiwan
4
Department and Graduate Institute of Electrical Engineering, Chang Gung University, Kwei-Shan, Taiwan 5
National Nano Device Laboratories, Hsinchu, Taiwan
6
United SOI Corporation, Berkeley, CA, 94707
7
Dept. of Physics, National Central University, Chungli, 320, Taiwan
8
Inst. of Materials Science and Engineering, National Central University, Chung-Li, Taiwan
ABSTRACT A fabrication method of 2-D nanostructure materials applied for forming nanothick SOI materials without using post-thinning processes is presented in this paper. The thickness of SOI layer is precisely controlled by a polysilicon layer as a sacrificial layer in the implantation step to acquire a desirable implant depth. Polysilicon layer was initially deposited on the thermal oxidized surface of silicon wafer prior to the ion implantation step with 4×1016 /cm-2, 160KeV, H2+ ions. The as-implanted wafer was contained a hydrogen-rich buried layer which depth from the top surface is less than 100 nm. Before this as-implanted wafer being bonded with a handle wafer, the polysilicon layer was removed by a wet etching method. A nanothick silicon layer was then successfully transferred onto a handle wafer under 10-minute microwave irradiation after the bonding step. The thickness of the final transferred silicon layer was 100 nm measured by transmission electron microscopy (TEM).
INTRODUCTION As CMOS devices are scaling down to 90 nm node or below, the phenomena of parasitic capacitance and current leakage become a serious issue. The unique electronic property of silicon-on-insulator (SOI) structure which consist of a top layer of quality single crystalline silicon on an insulating layer of SiO2 [1] to separate from the bulk silicon substrate is proposed to solve this kind of problems. Building IC devices in SOI layer provides lots of advantages such as
reducing parasitic capacitance and leakage and free from latch-up, especially for the requirement of high speed and low power consumption devices [2]. As the IC device is scaled down to nano degree, the thickness of SOI layer is also scaled down to have a 2-D nanostructure. SOI wafers at nanoscale thickness have now been widely accepted as an optimum choice of substrate for manufacturing nano-scale IC devices. Numerous advanced techniques for forming nanofilm have been invented nowadays [3] in SOI material fabrication. Among of them, the most widespread methods now for producing SOI materials are Smart-Cut® and SIMOX process. Smart-Cut® process which may be now the
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