200 mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions
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200 mm Silicon Wafer-to-Wafer Bonding with Thin Ti Layer under BEOL-Compatible Process Conditions J. Yu, J.J. McMahon, J.-Q. Lu, and R.J. Gutmann Focus Center – New York, Rensselaer: Interconnections for Hyperintegration Rensselaer Polytechnic Institute, Troy, New York 12180 Abstract Wafer level monolithic three-dimensional (3D) integration is an emerging technology to realize enhanced performance and functionality with reduced form-factor and manufacturing cost. The cornerstone for this 3D processing technology is full-wafer bonding under back-end-of-the-line (BEOL) compatible process conditions. For the first time to our knowledge, we demonstrate nearly void-free 200 mm wafer-to-wafer bonding with an ultra-thin Ti adhesive coating, annealed at BEOL-compatible temperature (400 °C) in vacuum with external pressure applied. Mechanical integrity test showed that bonded wafer pair survived after a stringent three-step thinning process (grinding/polishing/wet-etching) with complete removal of top Si wafer, while allowing optical inspection of bonding interface. Mechanisms contributing to the strong bonding at Ti/Si interface are briefly discussed. INTRODUCTION Wafer level three-dimensional (3D) integration is currently receiving wide spread attention from semiconductor industry [1, 2, 3, 4] and academia [5, 6], with International SEMATECH having identified 3D interconnect as a major technical challenge for 2005 [7]. The 3D structure offers opportunities for enhanced performance with reduced form-factor (e.g., for two-wafer stack, roughly 50% shorter global interconnect clock distribution and 50% smaller footprint compared to 2D architecture). Besides, it enables the extra degree of flexibility to integrate wafers fabricated by incompatible processes (for example, logic to memory, CMOS to BJT, CMOS to MEMS, and Si to III-V compound). The foreseeable drivers for the technology will be memory stacks, memory-intensive processors, smart imagers and mixed signal applications. Wafer-level 3D integration generally involves four major processing steps: 1) wafer-towafer alignment, 2) wafer-to-wafer bonding, 3) backside thinning, and 4) inter-wafer interconnection. A review on wafer-to-wafer bonding techniques could be found elsewhere [8]. Due to the constraints of compatibility with BEOL (≤450 °C) as well as concerns on contamination (e.g., no Na+ or Au+), the choices of wafer-to-wafer bonding are limited to metalbased wafer bond (for instance, copper-to-copper) [1, 4, 5], dielectric adhesive bond [6], and modified fusion bond (for example oxide-to-oxide) [2]. In addition to wafer-to-wafer mechanical attachment, metal-based wafer bonding offers better thermal management and direct electrical connection. Moreover, the metal bonding layer can be incorporated as an extra ground plane or power plane. In this work, we explore an alternative metal-based wafer bonding using ultra-thin titanium (Ti) as adhesive. For the first time to our knowledge, we demonstrate nearly void-free wafer-towafer bonding with blanket sputtered Ti, a
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