Nickel nano-dot arrays on silicon substrate fabrication and surface charge distribution
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MRS Advances © 2020 Materials Research Society DOI: 10.1557/adv.2020.180
Nickel nano-dot arrays on silicon substrate fabrication and surface charge distribution Anupam K.C.a Garrett Merrionb a
Materials Science, Engineering and Commercialization Program (MSEC), Texas State University, San Marcos, Texas 78666, United States
b
Department of Physics, Texas State University, San Marcos, Texas,78666, United States
ABSTRACT
We report a simple and feasible technique for the formation of well-distributed nickel nanodot arrays on both oxidized and unoxidized silicon substrate by a conventional annealing process. The shape and distribution of nickel nanodots were maintained by adjusting annealing temperature, time and the SiO2 buffer layer thickness in between nickel film and the silicon substrate. The diffusion of nickel into the silicon is significantly reduced when the nickel film on the oxidized silicon substrate is annealed at high temperature. From this conventional annealing technique, we achieve a maximum nickel nanodots density up to (7.94±1.92) nanodot counts/µm2 on the oxidized silicon substrate with a well-defined spherical shape by adjusting the thickness of nickel film as well as buffer SiO2 layer. In the next experiment, the surface charge distribution on the nickel nanodot arrays were characterized through the Kelvin probe force microscope (KPFM) on tapping mode. It is found that the nickel nanodots can store and release the electric charges under an applied bias voltage.
INTRODUCTION Nanometer-scale dot arrays on silicon substrates are of interest for applications in electronics [1], optoelectronics [2] and magnetic devices [3].In particular, the selfassembly of nickel nanodots on the silicon substrate for potential applications in field emission and biometric sensing has also driven research interest [4–6]. Many research groups have reported that rapid thermal annealing (RTA) causes nickel nanodots formation on a silicon substrate [7], while other researchers have investigated the welldistributed nickel nanodots on a silicon substrate with a thin buffer layer of SiO 2, Si3N4,
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TiN, etc., by using a general tube furnace [4,5]. Kuang et al. [4] have employed the conventional annealing process to fabricate silicon nano-pillars by Reactive ion etching (RIE) on the nickel nanodots mask on a silicon substrate. They have reported a wellformed nickel nanodots on RCA (Radio Corporation of America, a cleaning technique to remove contaminants from wafers) cleaned silicon substrate by a conventional annealing process. However, the limitation of their process is that the self-aggregation of nickel nanodots from the nickel film coated on the silicon substrate usually spends up to 15-60 min by thermal annealing at different temperatures in an N2 atmosphere. Similarly, Lin et al.
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