Noise Performance of High Fill Factor Pixel Architectures for Robust Large-Area Image Sensors using Amorphous Silicon Te
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0989-A14-05
Noise Performance of High Fill Factor Pixel Architectures for Robust Large-Area Image Sensors using Amorphous Silicon Technology Jackson Lai1, Yuri Vygranenko1, Gregory Heiler2, Nader Safavian1, Denis Striakhilev1, Arokia Nathan3, and Timothy Tredwell2 1 Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, N2L 3G1, Canada 2 Eastman Kodak Company, 1700 Dewey Avenue, Rochester, NY, 14650-1822 3 London Centre for Nanotechnology, University College London, London, WC1H OAH, United Kingdom ABSTRACT Large area digital imaging made possible by amorphous silicon thin-film transistor (a-Si TFT) technology, coupled with a-Si photo-sensors, provides an excellent readout platform to form an integrated medical image capture system. Major development challenges evolve around optimization of pixel architecture for detector fill factor, signal propagation performance, and manufacturability, while suppressing noise stemming from pixel array and external electronics. This work analyzes a novel vertically integrated pixel design based on signal readout and noise performance, and compares with conventional co-planar and continuous detector architectures. In addition, the analysis will consider various substrate options including glass and robust substrates such as polymer and metal foil. Our evaluation have demonstrated state-of-the-art radiographic detector system with electronic noise under 2000 electrons at 150 µs frame time for an imaging arrays on robust substrate. INTRODUCTION Large-area digital image sensors are revolutionizing medical imaging by enabling electronic storage capability, immediate feedback, and possibilities to support previously unachievable applications related to computer aided image processing. Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) technology, frequently used in liquid crystal display applications, is extended to perform back-plane readout for large-area detector system. Technological attributes of a-Si:H such as uniformity over large area, compatibility with various substrate material, and research maturity have provided an excellent development platform for high performance, low noise, and fully integrated digital detector system. In conventional imaging array design [1][2] where the thin-film transistor (TFT) and photo-sensor in a pixel are placed side by side on the same plane, the fill-factor, signal-to-noise ratio and dynamic range are limited. An alternative approach is a vertically integrated high fill factor architecture where the photo-sensor is implemented as segmented [1] or non-segmented continuous layer [2]. Vertically integrated architectures increases the fill factor to achieve higher detected quantum efficiency (DQE), leading to better signal-to-noise ratio and is crucial to applications with stringent signal specification such as medical imaging. Meanwhile, alternative substrates options such as conducting stainless steel for hosting aSi:H pixelated detector array has also gained considerable i
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