Nonvolatile Silicon Memory at the Nanoscale
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Nonvolatile Silicon Memory at the Nanoscale
Helena Silva, Moon Kyung Kim, Uygar Avci, Arvind Kumar, and Sandip Tiwari Abstract The key challenges for memories that operate at the nanoscale and that are compatible with mainstream semiconductor processing are in achieving the performance characteristics that make the integration of hundreds of millions or more of such devices feasible. The concept of harnessing a single electron or just a few electrons for memory storage is very appealing, but among the issues to address are the increased variance, smaller signal, and numerous other consequences of the reduced statistics resulting from reduced number of carriers employed. Coupling a few electrons to a transistor channel provides a structure with the power gain and the necessary current for fast memory-state detection as well as compatibility with mainstream processing. Several recent ideas, such as the use of nanocrystals and defects, and decoupling storage from the read process, provide paths to addressing the issues of power, speed, technology compatibility, and variability in these structures. We discuss several approaches to nanoscale nonvolatile silicon memory, their attributes, and the underlying materials issues, with a focus on finding the design compromises necessary to enable their manufacturability. Keywords: nanoscale memory, nonvolatile silicon memory, silicon technology, singleelectron effects.
Introduction Harnessing a few electrons in order to take advantage of their inherent low power has been of interest to developers of memory technologies for quite some time now. Semiconductors, when confined at the nanoscale—such as in quantum dots— provide a means to limit the number of electrons employed through the reduced number of states and reduced capacitance. A number of structures have provided the ability to use these effects as the basis of a memory element. However, the challenge to these approaches includes retaining compatibility with the evolutionary path of silicon electronics as chip dimensions continue to shrink, and maximizing reproducibility, speed, and power. Power has been a central issue of integration at high densities with shrinking dimensions, primarily because of the excessive temperatures that result, but also because of the device reliability and characteristics desired—that is, voltages and current MRS BULLETIN/NOVEMBER 2004
levels that can be sustained in the electronic environment. High voltages and currents lead to long-term reliability issues through defect generation and electromigration in addition to the increased temperatures of operation. Low power levels, with reduced voltage and current, can also be a problem. For example, low voltages result in limits to integration because the window of variability allowed in device characteristics for reproducible circuit operation shrinks as a result of reduced noise margin. Likewise, low currents result in slower speed due to the excessive time spent in capacitive charging of interconnections and the difficulties in the detection o
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