Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for L
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ORIGINAL PAPER
Novel Asymmetric Recessed-Gate/Source Architecture Advancement of Dual-Metal-Gate SiGe/Si Dopingless Nanowire-TFET for Low-Voltage Performance Optimization Naveen Kumar 1
&
Ashish Raman 1
Received: 24 April 2020 / Accepted: 18 August 2020 # Springer Nature B.V. 2020
Abstract A dopingless vertical Nanowire (NW) Tunnel Field Effect Transistor TFET structure has been designed using techniques such as Dual-Metal Gate (DMG), Heteromaterial Channel (HmC) and Heterodielectric Oxide (HdO) to enhance the device performance. The proposed device is investigated to acknowledge the device behavior for RF/Low-Noise applications. The essence of the reported work is to capture the effect of work function variation of DMG on device characteristics for noise enhancement/ degradation. The vertical structure simplifies the implementation of charge-plasma technique for induced doping within the source/drain region enveloped by Gate-All-Around (GAA) architecture. Different work function combinations of gate metal1 (GM1) and gate metal2 (GM2) are used for calculations and compared to acquire optimized results. Other than Silicon, SiliconGermanium compound (SixGe1-x) with composition factor (x) equals to 0.55 is used for HmC, whereas Zirconium Silicate is preferred for HdO. The characteristics analysis includes the negative drain bias variation that captures an interesting tunnel diode characteristics with peak current to valley current ratio of approx. 108. The proposed structure is modified to reduce the Gate-toSource capacitive coupling and drain current enhancement. The proposed device is analyzed for Ambipolar-state, OFF-state and ON-state, which is required to understand the proper working of TFET devices. Key words Dopingless . Dual-Metal-Gate . Heterodielectric Oxide . Heteromaterial Channel . Si0.55Ge0.45 Nanowire
1 Introduction The greater need for noise-free sensitive circuits [1, 2] require active device components with lower internal noise or device structure with noise-resistant characteristics [3, 4]. The progressive change of efficient circuit design [5] needs devices with better linearity [6] to reduce the number of external noise cancellation [7] and biasing blocks [8]. However, the scaling down of semiconductor devices imports several quantum effects [9, 10] that may vary the device characteristics. Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
* Naveen Kumar [email protected] Ashish Raman [email protected] 1
VLSI Lab, Department of Electronics and Communications, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar 144011, India
based nanodevices [11, 12] are susceptible to short channel effects [13] with higher OFF-state current [14]. A higher threshold voltage with body factor [15] being more dominant in MOSFET based devices restricts them to be used for low noise applications. It is harder to achieve the saturation of drain current [16] in nano-MOS devices due to the ballistic effect [17] of charge carriers with increment in carrier mobility. Tunnel Field Effect Transist
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