Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications
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https://doi.org/10.1007/s11664-020-08541-9 2020 The Minerals, Metals & Materials Society
Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications ANUBHA GOEL ,1,4 SONAM REWARI,2,5 SEEMA VERMA,3,6 and R.S. GUPTA1,7 1.—Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, GGSIPU, New Delhi, India. 2.—Department of Electronics and Communication Engineering, Delhi Technical University, New Delhi, India. 3.—Department of Electronics, Banasthali Vidyapith, Niwai, Banasthali, Rajasthan 304022, India. 4.—e-mail: [email protected]. 5.—e-mail: [email protected]. 6.—e-mail: [email protected]. 7.—e-mail: [email protected]
Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher Ids, gm, gd and fT compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing ION/IOFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (Rch), advanced early voltage (VEA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S21 and S12) and reflection coefficients (S11 and S22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs. Key words: Nanotube, dual-metal, junctionless, analog, MOSFET, short channel effects (SCE)
INTRODUCTION In recent years, revolutionary momentum has been seen in the silicon industry, and the evolution still remains never ending. Subsequently, in-depth concerns have spawned different architectures and devices in order to find the maximum level to which the devices can be scaled down for future ultra large-scale integrations (ULSI).1 It can be seen that, even in the deca-nanometer regime (sub-0.1 lm), many short channel effects (SCEs) like an increase in the subthreshold slope (SS), greatly affects the
(Received June 12, 2020; accepted September 29, 2020)
overall scalability of the device, demanding consideration.2 The potential of silicon technologies beyond the 100-nm regime has been well indicated by modeling and simulation.3–5 To combat the effects of SCEs, many variations of device designs have been recommended and studied by researchers. Gate all around (GAA) nanowire (NW) structures have been the most encouraging device structure for metal oxide semiconductor field-effect transistor
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