Threshold Voltage Performance of a-Si:H TFTs for Analog Applications
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Threshold Voltage Performance of a-Si:H TFTs for Analog Applications K.S. Karim, K. Sakariya, and A. Nathan Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L 3G1 Canada. ABSTRACT Amorphous silicon (a-Si:H) thin-film transistors (TFT) used in emerging, non-switch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (VT) stability performance. At small gate voltages (0 ≤ VST ≤ 15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain is found to decrease the shift in VT (∆VT) compared to the ∆VT in the absence of a drain bias. In this paper, a ∆VT model accounting for TFT drain bias, is used to predict the performance of a-Si:H analog circuits in active pixel sensor (APS) medical xray imaging and active matrix, organic light emitting diode (AMOLED) display applications. INTRODUCTION Unlike crystalline silicon transistors, a-Si:H TFTs exhibit bias induced metastability phenomena that can have adverse effects on circuit performance if the circuit is improperly designed or operated. The metastability concerns become particularly important when the TFT is used as an analog device. In contrast to traditional applications (e.g. in LCDs) where the TFT is used as a switch, analog applications require the device to withstand prolonged voltages on both drain and gate terminals. Defect state creation and charge trapping are the widely accepted mechanisms for VT instability in a-Si:H TFTs. Defect creation dominates at lower bias voltages while charge trapping in the gate insulator is dominant at higher biases. Low power requirements in emerging analog applications of a-Si:H TFT technology (e.g. APS x-ray imaging [1] and AMOLED display [2]) underscore the drive towards reducing circuit supply voltages to a level where defect state creation is the dominant ∆VT mechanism. This research focuses on developing an understanding of circuit performance when dc bias voltages are applied simultaneously at the TFT drain and gate terminals in analog a-Si:H circuits. THEORY Charge trapping occurs primarily in PECVD a-Si:N gate insulator TFTs where the high density of defects in the insulator can trap charge when the TFT gate undergoes bias stress [3][4]. In contrast, defect creation in the a-Si:H layer or at the a-Si:H/a-SiN interface due to a prolonged gate bias has some similarities to light induced defect creation [7] where the density of deep state defects increases. The point at which the charge trapping component of ∆VT overtakes defect state creation has been shown to be a function of the gate nitride stoichiometry [4][5] and usually occurs at larger voltages for nitrogen rich gate dielectrics [6]. When a positive bias is applied to the gate of an a-Si:H TFT, electrons accumulate and form a channel at the a-SiN/aSi:H interface where they predominantly reside in conduction band tail states [8]. These tail states have been identif
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