Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering
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Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering S. Priscilla Scarlet1 · N. Vinodhkumar2 · R. Srinivasan3 Received: 3 June 2020 / Accepted: 21 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The silicon nanotube field effect transistor (FET) is a tubular structure and has an inner gate and outer gate to control the channel. In this paper, the performance of a junctionless silicon nanotube FET is optimized using inner and outer gate engineering through 3D numerical TCAD simulations. The performance of the optimized devices is enhanced in terms of ON I current (ION), OFF current (IOFF), and I ON ratio. Appropriate work function and gate dielectric choices are suggested for the OFF
inner and outer gates to obtain optimized devices. The lowest IOFF and highest I ON ratio are obtained for devices with high I
OFF
inner and outer gate permittivity along with low inner and outer gate work function. Also, the highest ION is obtained for the device with the highest inner and outer gate dielectric permittivity with low outer and inner gate work function. The device optimized for ION (98.6% increase compared to reference device) with the corresponding IOFF better than the reference device can be used for high-power applications. Keywords Junctionless · Silicon nanotube · Work function · Dielectric · FET
1 Introduction A number of important approaches have been introduced for tackling the issue of short channel effects (SCE), including (1) multi-gate structures, (2) junctionless (JL) devices, (3) gate dielectric engineering, and (4) gate electrode work function engineering [1–5]. Several multi-gate structures, such as fin field-effect transistors (FinFETs), tri-gate FETs, gate-all-around FETs, and nanowire FETs, have already been explored in the literature [6–10]. In the advanced form of the multi-gate structures, the silicon nanotube field effect transistor (SiNT-FET) was introduced in 2012 [11, 12]. In the SiNT-FET, the tubular channel is controlled by inner and outer gates. Since the inner gate provides additional charge control, the channel is more controllable in the SiNT-FET * S. Priscilla Scarlet [email protected] 1
Department of ECE, CVR College of Engineering, Hyderabad, India
2
Department of ECE, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, India
3
Department of IT, SSN College of Engineering, Kalavakkam, India
device compared to other multi-gate structures. The fabrication process steps for the tubular devices have been discussed in previous works [12–14]. Whereas in the multi-gate structures, control over the channel is achieved by increasing the number of gates, in junctionless devices, the source/drain-channel doping gradient is removed, thereby achieving better SCE performance [15, 16]. Junctionless devices are of interest to the device community because of both their reduced fabrication complexity and better SCE performance. Numerous junctionless oper
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