Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects
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1079-N09-09
Numerical Analysis of Packaging-Induced Failures in Cu/Low-k Interconnects Aditya Pradeep Karmarkar1, Xiaopeng Xu2, Xiao Lin2, Greg Rollins2, Victor Moroz2, and XiWei Lin2 1 Synopsys (India) Private Limited, My Home Tycoon, 4th Floor, Block A, Begumpet, Hyderabad, 500016, India 2 Synopsys, Inc., 700, East Middlefield Road, Mountain View, CA, 94043 ABSTRACT With decreasing feature sizes for every technology node, multi-level metallization schemes that employ copper interconnects and low-k dielectrics are required to achieve the requisite circuit performance. Here, the effects of the mechanical stresses originating from the packaging process on Cu/Low-k interconnects are assessed. The impact of package defects on interconnect reliability is also analyzed. It is seen that the package reliability varies with underfill mechanical properties. The packaging process introduces global level stresses that propagate to the local, i.e. interconnect, level. Moreover, the package defects also have an adverse impact on the mechanical stresses in the metallization structure. The package defects alter the mechanical stresses in the metal lines and affect the reliability. The complex interaction between packaging process induced stresses, package level defects and mechanical properties of various materials is analyzed in order to create robust interconnect designs. INTRODUCTION The current trends in the microelectronics industry demand decreasing feature sizes and increasing integration densities at each technology node. For deep sub-micron devices, multilevel metallization schemes that employ copper interconnects and low-k dielectrics are required to achieve the requisite circuit performance and yield. However, Cu/low-k interconnects are susceptible to mechanical stress induced failures due to their low mechanical strength [1]. Mechanical stresses originating from a number of sources affect the Cu/low-k interconnect reliability. Mechanical stresses generated in the Cu/low-k structures during packaging pose significant reliability challenges due to chip-package interaction. The packaging process generates mechanical stresses at the global level; which permeate to the local level, i.e. interconnect level, and are responsible for reliability failures and yield loss [2] - [4]. In this paper, the impact of chip-package interaction on Cu/low-k reliability is examined. Here, an advanced FEM based 3D simulator is used to examine interface delamination in the package and mechanical failures in interconnects, along with the interaction between these phenomena [5]. The simulator generates the 3D structures by performing fabrication process steps as described in [5], and solves the partial differential equations following the standard FEM procedure. Various sources of mechanical stress are considered during the process steps. The simulator can also account for the viscoelastic behavior of various materials at the processing conditions, which results in improved simulation accuracy. The J-integral method is used to determine the eff
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