Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in
This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analo
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Nyquist AD Converters
This first part of the book is on ‘Nyquist AD Converters’, which, as the name suggests, refers to AD converters that can convert signals up to (or close to) the Nyquist frequency. Six chapters will focus on this, from different architecture points of view. The first two Chapters address the pipeline converter: the various steps of the search algorithm are mapped in time in a successive, serial way. The Chapter of Ahmed Ali, from Analog Devices, US, treats the generic aspects of a pipeline converter without sample-and-hold amplifier, and with calibration. A specific converter, made in 180 nm BiCMOS, with 1.8 V supply, 1 W power consumption, 300 MHz input bandwidth, 250 MS/s, >90 dB SFDR, and 76.5 dB SNDR, is described. The second Chapter, of Jan Mulder from Broadcom, The Netherlands, describes a pipeline converter based on the dual-residue principle, which makes the converter insensitive to gain of the residue amplifier, allowing low gain and thus low power, without calibration. Moreover, the converter described uses four pipes in time interleaved. It is made in 40 nm CMOS, with 1/2.5 V supply, 105 mW, 4 200 MS/s ¼ 800 MS/s, 12 bit resolution, and 59 dB SNDR. Next, we make a step to two other converter types: the successive approximation converter (the SAR) and the slope converter. Pieter Harpe, from imec/Holst and University of Technology, Eindhoven, The Netherlands, discusses the alternative approach that starts from the inherently low power but low speed direction, choosing the SAR or slope converter, and then achieving speed by using time interleaving, so parallellization in time. A comparison between the SAR and the slope is given. This time-interleaving requires accurate timing. In his case this is achieved intrinsically, by using a proper architecture and layout. The Chapter of Erwin Janssen, from NXP, The Netherlands, uses massive parallellization via time interleaving of SARs, combined with a special open loop sampler that uses the same buffer in sampling and conversion phase to compensate non-linearities, a reduced radix in the SAR, and a redundancy in the number of SARs, to achieve a 2.6 GS/s, 10b conversion for DOCSIS type of multi-stream applications. The time interleaving is done in two steps to make a proper tradeoff in parallellization and sampling issues.
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I Nyquist AD Converters
The last two speakers discuss high speed converters above 10 GS/s. Jieh-Tsorng Wu, from National Chiao Tung University, Taiwan, describes the use of flash converters, the ultimate high speed architecture, in a time-interleaved way, to further boost the speed up to a 16 GS/s, 1.5 V, 435 mW converter with an SNDR of 38 dB. He uses regenerative latches that are randomly chopped to reduce the input referred offset, as an alternative to the use of power hungry preamplifiers, and a timing skew calibration detection and correction technique based on equal zerocrossing probability, in background, with extra replica samplers in each AD. Finally, Yuriy Greshishchev from Ciena Corporation, Canada, discuss
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