Optical Filter for Fabricating Self-Aligned Amorphous Si TFTS
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utilized as the etch-stop to form the source/drain electrode (Fig. 1). As a result, there are overlaps of the source/drain electrodes with the channel region, causing an extra parasitic capacitance between the gate and the source/drain electrodes. The high parasitic capacitance results in a feed-through voltage on the pixel electrode, producing image flicker and sticking [1].
Overlap
Opening
Self-aligned TFT 100/ ---- - - -----.--
-
-
Contact
Vlk•
Conventional TFT
-
>
Substrate
Channel Length (a.u) Figure 1. Device structure of a conventional bottom-gate a-Si TFT.
Figure 2. Sketch of the manufacturing yield as a function of the channel length for conventional and self-aligned a-Si TFTs.
677 Mat. Res. Soc. Symp. Proc. Vol. 557 ©1999 Materials Research Society
Also, the overlap introduces a variation of the parasitic capacitance among the pixels, resulting in non-uniform gray-level performance. In addition to the problem of the parasitic capacitance, the non-self-aligned structure limits scaling down the channel length. The following analysis describes how the yield of large-area manufacturing process is affected by scaling the channel length. In the conventional manufacture process for the bottom-gate a-Si TFTs, the yield for the channel length definition is governed by: Y=
(1)
op* Y., * Yetch * Y,,f
where yop is the yield factor related to the opening between source/drain contacts, y., is the factor of the alignment accuracy of the source/drain contact versus the passivation island, yetch is the factor related to the etching accuracy of the source/drain contact, and yetf is the factor related to the formation of the self-aligned passivation island. All of these factors, except y.cjf, depend on
the channel length. As depicted in Fig. 2, that the manufacturing yield decreases with the reduction of in channel length. This problem can be alleviated by forming self-aligned source/drain contacts with a pulsed laser doping technique [2]. A difficult challenge in making self-aligned TFT structures is the necessity of making source/drain contacts that exhibit low contact resistances and that are precisely aligned relative to the gate electrode. In this paper, we describe a novel process which utilizes a pulsed excimer laser (308 nm) to dope or to activate dopants in a-Si to form the source/drain contacts. An important feature of the device design is an optical filter to protect the a-Si channel region from radiation damage during the 308 nm laser process. However, the optical filter allows the transmission of the uv light for lithography exposure from the backside of the substrate to align the channel region with the gate electrode. This process not only reduces the TFT parasitic capacitance, but also improves the yield factor by avoiding yield factors of yop, y.1, and yeth in formula (1) (Fig. 2). PROXIMITY LASER DOPING TECHNIQUE Excimer Laser ,'*#
-
Doping Film
Gap
Surface Region Melted by Laser
Figure 3. Schematic of the proximity laser doping technique [3].
678
We developed a large-area elect
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