Optimized Ultrasharp Silicon Nanowire Geometries for Enhanced Field Ionization Properties
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Optimized Ultrasharp Silicon Nanowire Geometries for Enhanced Field Ionization Properties Kazim Gurkan Polat1, Chen Zhou1, Ahmad Umar2 and M. Saif Islam1 1
Department of Electrical and Computer Engineering, University of California - Davis, Davis, CA 95616, USA
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Department of Chemistry, Najran University, Najran 11001, Saudi Arabia
ABSTRACT Silicon (Si) nanowires offer great potential for field ionization (FI) applications due to well-established Si microfabrication methods combined with favorable ionizing properties of Si. Band bending of semiconductors under applied electric fields increases the FI probability, which is not possible with metal-based counterparts. While it has been demonstrated that scaling down the active material geometry can increase the FI efficiency, maximum electric field at the tip of a single nanowire decreases by quenching effect of nearby nanowires. In this work, optimization of Si nanowire geometries for improved FI efficiencies is explored. INTRODUCTION The ionization of gas molecules is important for many applications such as gas sensing and removal of pollutants in environment, building and power plants. Therefore, there is a need for efficient field ionization devices, in which advanced material and fabrication techniques play an instrumental role in this field. Under high electric fields (~ 3e7 V/cm) [1], FI process ionizes neutral gas molecules or atoms by tunneling of one of their valence electrons bound by a potential well into the vacuum or unoccupied states available at the surface of solid materials [2]. Conventional gas ionization systems consist of metallic needles, which are limited by their bulky architecture requiring high power consumption and risky high operating voltages [3]. The objective of this paper is to model and demonstrate the engineered Si nanowire geometries that can enhance the FI properties more than several hundred folds by controlling the periodicity, diameter and height of the nanowires, as well as the distance between the electrodes. EXPERIMENTAL Fabrication Two different random nanowire geometries were fabricated using top-down and bottom-up approaches for comparison. Top-down nanowire geometries were fabricated with electroless etch (EE) technique and bottom-up nanowire arrays were grown with vapor-liquid-solid (VLS) technique using chemical vapor deposition (CVD). EE nanowires were fabricated on p-Si (100) wafer through Ag-assisted etching technique. Prior to etching process samples were cleaned for 15 minutes in piranha solution (mixture of hydrogen peroxide and sulfuric acid), rinsed in deionized (DI) water, and dried with nitrogen. Then samples were immersed into a solution consisting of hydrofluoric acid (HF) and silver
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nitrate (AgNO3) with concentration of 4.6 M and 0.02 M, respectively [4]. Temperature and etching time were selected as 25 oC and 60 minutes, respectively. CVD grown nanowires were fabricated on p-Si (111) wafer using VLS technique. Precleaned Si samples were covered by 3 nm thin Au layer by e-beam deposition. Then, samp
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