Oversampling A/D Converters with Improved Signal Transfer Functions
This book describes techniques for designing complex, discrete-time ΔΣ ADCs with signal-transfer functions that significantly filter interfering signals. The book provides an understanding of theory, issues, and implementation of discrete complex ΔΣ
- PDF / 15,766,929 Bytes
- 200 Pages / 439.37 x 666.142 pts Page_size
- 67 Downloads / 152 Views
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University
For further volumes: http://www.springer.com/series/7381
Bupesh Pandita
Oversampling A/D Converters with Improved Signal Transfer Functions
Bupesh Pandita AMD Markham, ON, Canada [email protected]
ISBN 978-1-4614-0274-9 e-ISBN 978-1-4614-0275-6 DOI 10.1007/978-1-4614-0275-6 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011934486 # Springer Science+Business Media, LLC 2011
All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Abstract
This book proposes a low-IF receiver architecture suitable for the realization of single-chip receivers. To alleviate the image-rejection requirements of the frontend filters an oversampling complex discrete-time DS ADC with a signal-transfer function that achieves a significant filtering of interfering signals is proposed. A filtering ADC reduces the complexity of the receiver by minimizing the requirements of analog filters in the IF digitization path. Discrete-time DS ADCs have precise resonant frequency and clock frequency ratios and, hence, do not require the calibration or tuning that is necessary in the case of continuous-time DS modulator implementations. This feature makes the proposed discrete-time DS ADC ideal for multistandard receiver applications. The DS modulator signal-transfer function (STF) and noise-transfer function (NTF) have been designed using complex filter routines based on classical filter design procedures. With a filtering STF and stop band attenuation greater than 30 dB, the DS modulator reduces intermodulation of the desired signal and the interfering signals at the input of the quantizer, and also avoids feedback of the high-frequency interfering signals at the input of the modulator. The reported complex DS ADC is intended for DTV receiver applications. With a maximum intended sampling frequency of 128 MHz and an OSR of 16, the ADC has been designed to support a maximum DTV signal bandwidth of 8 MHz. Except for a somewhat reduced maximum sampling frequency, the test results of the prototype complex DS modulator are very close to the simulated results. The IC achieved 70.9 dB SNDR over a 6 MHz band centered around 3 MHz. The image rejection ra
Data Loading...
