Parallel Pseudo-Exhaustive and Low Power Delay Testing of VLSI Systems
The aim of the paper is to conduct parallel delay testing of modules with different input capacities in a SOC, using mutual BIST pattern generator; especially iterative system realisations well suited for VLSI fabrication technologies. The quality of timi
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Parallel Pseudo-Exhaustive and Low Power Delay Testing of VLSI Systems Deepa Jose and P. Nirmal Kumar
Abstract The aim of the paper is to conduct parallel delay testing of modules with different input capacities in a SOC, using mutual BIST pattern generator; especially iterative system realisations well suited for VLSI fabrication technologies. The quality of timing optimised and high performance digital VLSI systems is assured only through delay testing. A unique accumulator based Iterative PseudoExhaustive Two-Pattern (IPET) generator for parallel delay BIST is presented. Generally, the accumulator belongs to the data-path of the SOC. Hence, IPET test can be generated using micro-code self-test strategy. Reduced hardware overhead due to accumulator based design and test time due to parallelism is found to be beneficial. A CMOS implementation of Low Power Architecture for delay testing is carried out, which reduces test power and test time. These architectures can be used as efficient chip-level designs for high speed and low power BIST of SOCs. Keywords Delay testing exhaustive test
Parallel BIST Low power Digital VLSI Pseudo-
D. Jose (&) P. N. Kumar Department of Electronics and communication Engineering, Anna University, Chennai, India e-mail: [email protected] P. Nirmal Kumar e-mail: [email protected]
V. V. Das (ed.), Proceedings of the Third International Conference on Trends in Information, Telecommunication and Computing, Lecture Notes in Electrical Engineering 150, DOI: 10.1007/978-1-4614-3363-7_45, Springer Science+Business Media New York 2013
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D. Jose and P. Nirmal Kumar
45.1 Introduction The advent of nanotechnology has massively increased the density and operating frequency of the SOC. Iterative system realisations, which consist of interconnected modules, currently gain more importance in the modern high-speed digital systems. Iterative systems are well suited for VLSI fabrication technologies and offer advantages like ease of bypassing faulty cells, high flexibility in design, function and performance, and its close resemblance with Field Programmable Gate Array (FPGA). Pseudo-Exhaustive testing of repetitive structures like Multipliers, Adders, FFT processors, Bit-sliced microprocessors, Iterative Logic Arrays (ILAs), Digital Signal Processing systems, Data-path architectures and Embedded Memories require special set of test patterns in the BIST environment. For such complex VLSI circuits with large number of inputs (n), exhaustive testing requires 2n test patterns and the test time increases exponentially with n. For a (n,m,k)-CUT with n-inputs, m-outputs and cone-size k, the Pseudo-exhaustive testing approach involves applying exhaustive test to the m-output cones. In such cases Pseudoexhaustive testing objectives can be formulated so that the entire n-bit space will be exhaustively covered, if for all n-k ? 1 contiguous k-bit subspaces, each of the 2k patterns occur at least once [1, 2]. This modified scheme is called as Recursive Pseudo-Exhaustive (RPE) testing.
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