Planarization Specification for 22nm and beyond BEOL CMP
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Planarization Specification for 22nm and beyond BEOL CMP Jihong Choi1, Changan Wang1, Yayi Wei1, Eden Zielinski1, Wei-tsu Tseng2, Yongsik Moon1, Mark Kelling1, Laertis Economikos2 1
GLOBALFOUNDRIES, 2070 Route 52, Building 300, MS A-10, Hopewell Junction, NY 12533 2 IBM Microelectronics, 2070 Route 52, Building 300, MS A-10, Hopewell Junction, NY 12533 ABSTRACT This study discusses topography specifications for 22 nm and beyond CMP process and presents recent experimental data. We evaluated local topography impact on CD development in the subsequent layer using specially designed 22-nm test patterns. A wide range of localized erosions were generated in CMP within a single exposure field to avoid any focus-correction effect by the scanner or any other scanner-induced focus change between different levels of local erosion. Local erosions were measured by atomic force microscopy (AFM) after each process step from CMP to lithography to identify the local planarization effect from other film coatings between CMP and lithography. Post-litho CD inspection was done in the subsequent layer over the local erosion areas. Using experimental results, the paper also discusses BEOL pattern design rule for maximizing the process window. INTRODUCTION In logic IC manufacturing, more than ten interconnect metal layers are used in many applications [1]. Layers of several different metal pitches and minimum critical dimensions (CDs) are used, and how to stack those layers depends on the chip application and design requirement for R and C. Small pitch layers (thin wire) with a tight lithographic depth of focus (DOF) requirement are formed first, and larger pitch layers (fat wire) with more room for DOF are formed later, on top of thin-wire layers. Hence, topography specification for top metal layers can be less aggressive even though those layers have larger topography than lower layers. However, in many logic applications using sub-32-nm technology nodes, more than five thin wire layers are required, and prediction of process feasibility for back-end-of-line (BEOL) metal layers stack options is critical in the process development stage. Since CMP is one of the last process steps before lithography that is directly related to the planarization of wafer surface, CMP topography specification is a key parameter to characterize the feasibility of a given BEOL stack option. CMP-induced topography is systematic largely in three different lateral scales: wafer scale, die scale, and feature scale. Wafer-scale topography variation is from the radial dependency of the CMP process. Die-scale variation is from the effective pattern density effect across a chip, which is the domain of design for manufacturing (DFM) [2, 3, 4]. Feature-scale topography is individual line width-, line space-, or feature shape-dependent variation. Waferand chip-scale variation can be compensated for in the lithography scanner through focus-level adjustment by measuring wafer surface heights before each exposure. Today, optical or mechanical detection of lon
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