Cu CMP and its Challenge for 20nm Nodes and Beyond
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Cu CMP and its Challenge for 20nm Nodes and Beyond John H. Zhang1*, Wei-Tsu Tseng2, Laertis Economikos2, Qiang Fang3, Jianping Zheng3, Lin Yang2, Donald F. Canaperi4, Michael Lofaro5, Ben Kim1, Chao-Kun Hu5, Eric G. Liniger5, Richard Murphy2 , Tsong L. Leo Tai2, Walter Kleemeier1, Cindy Goldberg1, Jennifer Muncy2, Xiaomeng Chen2, and Ron Sampson1 1
STMicroelectronics, 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. IBM Semiconductor Research and Development Center (SRDC), 2070 Route 52, Hopewell Junction, NY 12533, U.S.A 3 GLOBALFOUNDRIES, 2070 Route 52, Hopewell Junction, NY 12533, U.S.A. 4 IBM at Albany Nanotech, Albany, NY 12203, USA 5 IBM Research, Yorktown Heights, NY 10598, USA *Email: [email protected], [email protected] 2
ABSTRACT The challenges associated with meeting 20nm technology requirements for better Cu CMP process uniformity and lower defectivity have been studied. Required improvements in uniformity were obtained through platen process optimization along with evaluation & selection of specific Cu slurries and pads and their performance reported. The principal factors influencing defect formation, including Cu barrier metallurgy, interconnect pattern density and process queue times were studied. Specific new post CMP clean chemistries were evaluated to assess their capability to suppress defect formation and their performance reported. The trade off between uniformity and defect suppression as a function slurry, pad and post Cu CMP clean chemistry is described. INTRODUCTION As interconnect dimensions continue to shrink with each successive new technology node, it is necessary to further improve Cu CMP uniformity while suppressing defectivity to lower target levels for yield improvement and reduced resistance variability for RC center. This challenge is complicated by an increase in sensitivity of the CMP process to incoming wafer pattern density and topography, where wafer topography and associated systematic processinduced variation can be categorized using three different lateral scales: wafer scale, die scale, and feature scale [1]. At 20nm technology dimensions, CMP uniformity and variation control become critical at all three of these scale levels. There are several specific challenges to uniformity. When combined with advanced integration schemes that include thinner hard mask and barrier metal layers, current slurries may not be adequate. Reduction in hard mask thickness reduces the planarization requirement, but increases polish rate sensitivity to pattern density, which can lead to Cu dishing. CMP processes must minimize dishing yet also be able to remove Cu material from low-lying areas associated with prior level topography. Thinner barriers are susceptible to increased erosion by the copper slurry, particularly in dense arrays, which can lead to an increase in the variation of the interconnect resistance [2]. Pattern density variation effects incoming to CMP can be further aggravated by copper “mounding” over dense arrays due to the
type of plating chemistries used. Reactive ion et
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