Analysis of CMP planarization performance for STI process
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Analysis of CMP planarization performance for STI process
Manabu Tsujimura,Ebara Corporation, Deputy Group Executive, Precision Machinery Group NISSEI AROMA SQUARE 5-37-1 Kamata Ohta-ku Tokyo Japan Fax & e-mail: 81-3-5714-6670 81-3-5714-6081 [email protected] Co-authors: < Hisanori Matuo, Hirokuni Hiyama,Ebara >< Masahiro Ota, Dr.Eng. Tokyo Metropolitan University>
ABSTRACT It has recently been reported that some waviness may affect STI CMP yield. CMP is designed primarily to planarize relatively with large r scale than small topography. However, there may be a range of wafer topographies in which STI patterns are over-polished, depending on peak-to-valley variations and frequencies. Permissible peak-to-valley variations and frequencies are calculated by determining whether the difference in polish quantities between the peak and valley is less than permissible values, such as 10 nm, 20 nm, and 30 nm. Reports indicate that slurry selectivity can decrease this effect, although with certain disadvantages. INTRODUCTION As shown in the International Technology Roadmap for Semiconductors, the history of semiconductor device may be characterized by the two trends of finer node scaling and larger wafer size scaling. CMP has been adopted not only for ILD and W-plug, but for Cu metals and STI. In the STI CMP process, although the wafer displays some defined waviness, and it has recently been reported that some waviness affect STI CMP yield. Since CMP is intended to planarize relatively large topographies, there may be a range of wafer topographies in which the STI pattern may be over-polished, depending on peak-to-valley variations and frequencies. The range and dishing performance of STI are calculated based on step height performance, which is in turn calculated by FEM. ANALYSIS 1 Nanotopography and CMP planarization performance for STI As shown in Fig. 1, CMP in this analysis is defined as four types of regions. The first region, called the step height region, requires planarization performance of step height reduction. The second region, the uniform material region, requires uniform polish. The third region, the non-uniform material region, requires planarization performance of dishing and erosion reduction. The fourth region, the substrate region, requires defect reductions. STI CMP is required to decrease the range in the stopper layer within the wafer and the dishing, as shown in Fig-2. In this example, polishing rates are highest in the center M3.6.1
position and lowest at the edge. When the silicon oxide on the stopper layer has been completely cleared, the center position has the largest polish value, i.e. the range and the dishing attain their highest values. These values depend on polishing non-uniformity within the wafer and the selective ratio of the slurries. Total Oxide Loss Dishing
Range in wafer
CMP-1 CMP-2 CMP-3 CMP-4
Lowest polish in edge ILD
Highest polish in center
Wafer STI
Metal
SiO2 Stopper Si-substrate
Fig.1 CMP regions model
Fig. 2 STI process
As shown in Fig. 3, wafer wavines
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