Power Delivery, Signaling and Cooling for 3D Integrated Systems
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Power Delivery, Signaling and Cooling for 3D Integrated Systems Muhannad S. Bakir1 and Gang Huang2 1 2
Georgia Institute of Technology, {[email protected]} Was with Georgia Institute of Technology, currently with Intel
ABSTRACT Three-dimensional (3D) integration of ICs provides unique opportunities to improve bandwidth, latency, and power dissipation bottlenecks of interconnects (both on- and off-chip). However, while 3D IC integration improves signal interconnection, it also presents new challenges, especially in power delivery and cooling (“thermal interconnects”). The focus of this paper is on some of the key challenges and promising technologies to address power delivery, cooling, and signaling in a 3D stack of logic ICs.
INTRODUCTION The information revolution has been the most important economic event of the past century and its most powerful driver has been the silicon integrated circuit (IC). Over the past fifty years, the migration from BJT to CMOS technology combined with transistor scaling has produced exponential benefits in microchip productivity and performance. However, as gigascale silicon technology progresses beyond the 45 nm node, the performance of a system-on-a-chip (SoC) has lagged by progressively greater margins to reach the “intrinsic limits” of each particular generation of technology. A root cause of this “lag” is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC, especially in areas of cooling [1-4], off-chip signaling [2, 3, 5-7], and power delivery [1, 2, 7]. The need for ever greater off-chip bandwidth will be especially problematic as the number of cores on a microprocessor increases [5, 7, 8]. Revolutionary silicon ancillary technologies are needed to address these challenges. Of course, innovation in silicon ancillary technologies will have to be done in parallel with continued innovations at the chip level (improved scaled transistors and interconnects) as well as system architecture among other things [7, 9]. Three-dimensional system integration can be used either to (for example) partition a single chip into multiple strata to reduce on-chip global interconnect length [10] and/or used to stack chips that are homogenous or heterogeneous. An example of 3D stacking of homogenous chips is memory chips, while an example of heterogeneous chip stacking is memory and microprocessor chips. However, while 3D technology can be used to enhance communication between ICs (larger bandwidth, lower latency, and lower energy per bit), it also presents a number of challenges. Aside from issues relating to manufacturing, power delivery [11] and cooling [3] of a stack of logic chips presents many challenges. Simply put, it is difficult enough to cool and deliver power to a single processor today. Stacking multiple processors and memory
chips, for example, presents formidable challenges that require adva
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