Probing Effects of Etching Plasmas on the Properties of Porous Low-k Dielectrics
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Probing Effects of Etching Plasmas on the Properties of Porous Low-k Dielectrics L. Wang, J. Liu, W.D. Wang, and D.Z. Chi* Institute of Materials Research & Engineering, 3 Research Link, Singapore 117602 D. W. Gidley Department of Physics, University of Michigan, Ann Arbor, Michigan 48109 A. F. Yee Department of Chemical Engineering & Materials Science, University of California, Irvine, CA 92697-2800
Abstract The application of porous low-k interlayer dielectrics is needed for reducing the parasitical capacitance, especially at 65-nm node and beyond. The understanding of process-induced modifications to material properties is crucial for a successful integration of these low-k dielectrics. The dry etching processes of porous low-k materials are important modules in ULSI fabrication. In this study, the interaction between MSQ-based JSR LKD-5109 films (shown by PALS to have interconnected 2.8 nm size pores) with CF4/O2 plasma has been investigated. Various ratios of O2 content were designed to characterize its effects on the etch rate, formation of polymerization layer, and properties of the LKD-5109 film. Composition analysis was conducted by SIMS and FTIR. Moisture absorption and fluorine diffusion into low-k films after etch process are observed, along with carbon depletion near the surface region. The influence of etching chemistries on the morphological characteristics of thin Ta barrier layers (8-nm in thickness) deposited on etched low-k films were further investigated by SEM, and it is found that oxygen concentration has significant influences on the morphological characteristics of thin Ta barriers. 1. Introduction The size scaling in IC technology poses great challenges for back-end-of-line (BEOL) interconnect as the resistance-capacitance (RC) delay becomes a major limitation for the device performance. To address this issue, major changes must be implemented at each generation: copper metallization was first introduced to reduce interconnect line resistance, and low-k dielectrics were developed to reduce the parasitic capacitance [1]. To further meet the interconnect technology requirement outlined in International Technology Roadmap for Semiconductors 2003 (k
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